A system and method is provided to accurately model bidirectional wire I/O using hardware description language (HDL). The preferred model and method uses an HDL model that provides two parallel paths between ports of the bidirectional wire I/O. During simulation, the ports are monitored for activity. When an event is detected on either port, the model checks both ports to see if they are different values. If the ports are different values, one of the two parallel paths is enabled and the other disabled. For example, the model enables the path in which the new signal has appeared and thus passes the signal to the other port. The preferred model allows for the use of HDL elements that support full timing annotation. The preferred embodiment also removes the possibility of high impedance transition error that can result from false transitions to a high impedance state.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A model for representing a bidirectional wire input/output (I/O) during computer simulation of an electronic device, the model being tangibly embodied in a computer readable memory unit that comprises a Hardware Description Language (HDL) application program therein, the model being adapted to be used in a computer simulation of the electronic device by executing the HDL application program on a processor of a computer system, the model comprising: a) a first path between a first port and a second port, the first path including a second NMOS device; b) a second path between the second port and the first port, the second path including a first NMOS device; and c) a control mechanism, the control mechanism checking signal values (S 1 ) on the first port and signal values (S 2 ) on the second port when a change is detected on the first port or the second port, the control mechanism enabling the second NMOS device when a change is detected on the first port and the first port does not equal the second port, the control mechanism enabling the first NMOS device when a change is detected on the second port and the first port does not equal the second port, wherein the second path further includes a third NMOS device and wherein the first path further includes a fourth NMOS device, wherein the third and fourth NMOS devices are tied on to function as pass data-devices, wherein the first path and second path are electrically in parallel, wherein the second NMOS device and the fourth NMOS device are electrically in series within the first path, wherein the first NMOS device and the third NMOS device are electrically in series within the second path, wherein the gates of the third and the forth NMOS devices are held high throughout the computer simulation of the electronic device, wherein the control mechanism comprises a first control output C 1 directly coupled to the gate of the first NMOS device and a second control output C 2 directly coupled to the gate of the second NMOS device, wherein the signal values (S 1 ) at the first port are directly coupled to a source/drain of the first NMOS device, and wherein the signal values (S 2 ) at the second port are directly coupled to a source/drain of the second NMOS device.
2. The model of claim 1 , wherein a state of an NMOS device selected from the group consisting of the first NMOS device and the second NMOS device is dictated by the following truth table, wherein if the NMOS device is the first NMOS device then S denotes the signal values S 1 and C denotes the control output C 1 , and wherein if the NMOS device is the second NMOS device then S denotes the signal values S 2 and C denotes the control output C 2 , wherein L, denotes low, H denotes high, Z denotes high impedance, and X denotes undetermined: C 0 1 X Z S 0 Z 0 L L 1 Z 1 H H X Z X X X Z Z Z Z Z.
3. The model of claim 1 , wherein the model is implemented in the VHDL hardware description language using Vital timing routines.
4. The model of claim 1 , wherein the control mechanism enables the first path by enabling the second NMOS device when a change is detected on the first port and the first port does not equal the second port, and wherein the control mechanism enables the second path by enabling the first NMOS device when a change is detected on the second port and the first port does not equal the second port.
5. The model of claim 1 , wherein the timing values are annotated into the model in the form of module input port delays annotated into the third NMOS device and the fourth NMOS device.
6. The model of claim 1 , wherein the timing values are annotated into the model in the form of propagation delays across the first path and the second path.
7. The model of claim 1 , wherein the control mechanism further disables the first NMOS device when a change is detected on the first port and the first port does not equal the second port, and wherein the control mechanism further disables second NMOS device when a change is detected on the second port and the first port does not equal the second port.
8. The model of claim 1 wherein the control mechanism uses HDL register values to detect the change on both the first port and the second port.
9. A method for representing a bidirectional wire input/output (I/O) during a computer simulation of an electronic device, the method comprising: a) providing a model for the bidirectional wire I/O, the model including: i) a first path between a first port and a second port; and ii) a second path between the second port and the first port; b) checking signal values (S 1 ) on the first port and signal values (S 2 ) on the second port when a change is detected on the first port or the second port; c) enabling the first path when a change is detected on the first port and the first port does not equal the second port; d) enabling the second path when a change is detected on the second port and the first port does not equal the second port, wherein the model further includes a second NMOS device and a fourth NMOS device in the first path and further includes a first NMOS device and a third NMOS device in the second path, wherein the first path and the second path are electrically in parallel, wherein the second NMOS device and the fourth NMOS device are electrically in series within the first path, wherein the first NMOS device and the third NMOS device are electrically in series within the second path, wherein the gates of the third and fourth NMOS devices are held high throughout the computer simulation of the electronic device, wherein the control mechanism comprises a first control output C 1 directly coupled to the gate of the first NMOS device and a second control output C 2 directly coupled to the gate of the second NMOS device, wherein the signal values (S 1 ) at the first port are directly coupled to a source/drain of the first NMOS device, and wherein the signal values (S 2 ) at the second port are directly coupled to a source/drain of the second NMOS device.
10. The model of claim 9 , wherein a state of an NMOS device selected from the group consisting of the first NMOS device and the second NMOS device is dictated by the following truth table, wherein the NMOS device is the first NMOS device then S denotes the signal values S 1 and C denotes the control output C 1 , and wherein if the NMOS device is the second NMOS device then S denotes the signal values S 2 and C denotes the control output C 2 , wherein L denotes low, H denotes high, Z denotes high impedance, and X denotes undetermined: C 0 1 X Z S 0 Z 0 L L 1 Z 1 H H X Z X X X Z Z Z Z Z.
11. The method of claim 9 , further comprising the steps of: e) disabling the second path when a change is detected on the first port and the first port does not equal the second port; f) disabling the first path when a change is detected on the second port and the first port does not equal the second port.
12. The method of claim 9 , further comprising the step of annotating timing values across the first path and the second path.
13. The method of claim 9 , further comprising the step of annotating module input port delays into the third NMOS device and the fourth NMOS device.
14. The model of claim 9 , wherein the control mechanism uses Hardware Description Language (HDL) register values to detect the change on both the first port and the second port.
15. A program product comprising: A) a hardware description language model representing a bidirectional wire input/output (I/O) during a computer simulation of a electronic device, the hardware description language model including: i) a first path between a first port and a second port; ii) a second path between the second port and the first port; and iii) a control mechanism, the control mechanism checking signal values (S 1 ) on the first port and signal values (S 2 ) on the second port when a change is detected on the first port or the second port, the control mechanism enabling the first path when a change is detected on the first port and the first port does not equal the second port, the control mechanism enabling the second part when a change is detected on the second port and the first port does not equal the second port; B) recordable media hearing the hardware description language model, wherein the first path comprises a second NMOS device and a fourth NMOS device, and wherein the second path comprises a first NMOS device and a third NMOS device, wherein the first path and the second path are electrically in parallel, wherein the second NMOS device and the fourth NMOS device are electrically in series within the first path, wherein the first NMOS device and the third NMOS device are electrically in series within the second path, wherein the gates of the third and fourth NMOS devices are held high throughout the computer simulation of the electronic device, wherein the control mechanism comprises a first control output C 1 directly coupled to the gate of the first NMOS device and a second control output C 2 directly coupled to the gate of the second NMOS device, wherein the signal values (S 1 ) at the first port are directly coupled to a source/drain of the first NMOS device, and wherein the signal values (S 2 ) at the second port are directly coupled to a source/drain of the second NMOS device.
16. The model of claim 15 , wherein a state of an NMOS device selected from the group consisting of the first NMOS device and the second NMOS device is dictated by the following truth table, wherein if the NMOS device is the first NMOS device then S denotes the signal values S 1 and C denotes the control output C 1 , and wherein if the NMOS device is the second NMOS device then S denotes the signal values S 2 and C denotes the control output C 2 , wherein L denotes low, H denotes high, Z denotes high impedance, and X denotes undetermined: C 0 1 X Z S 0 Z 0 L L 1 Z 1 H H X Z X X X Z Z Z Z Z.
17. The program product of claim 15 , wherein the model is implemented in the VHDL hardware description language using Vital timing routines.
18. The program product of claim 15 , wherein the control mechanism enables the first path by enabling the second NMOS device when a change is detected on the first port and the first port does not equal the second port, and wherein the control mechanism enables the second path by enabling the first NMOS device when a change is detected on the second port and the first port does not equal the second port.
19. The program product of claim 15 , wherein the first NMOS device, the second NMOS device, the third NMOS device, and the fourth NMOS device comprise Verilog NMOS primitives.
20. The program product of claim 15 , wherein timing values are annotated into the model that include module input port delays annotated into the third NMOS device and the fourth NMOS device.
21. The program product of claim 15 , wherein timing values are annotated across the first path and the second path.
22. The program product of claim 21 , wherein the timing values are annotated in the form of propagation delays annotated between the first port to the second port and between the second port to the first port.
23. The program product of claim 15 , wherein the control mechanism further disables the second path when a change is detected on the first port and the first port does not equal the second port, and wherein the control mechanism further disables the first path when a change is detected on the second port and the first port does not equal the second port.
24. The model of claim 15 , wherein the control mechanism uses Hardware Description Language (HDL) register values to detect the change on both the first port and the second port.
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May 11, 2001
January 10, 2006
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