A semiconductor package device includes an insulative housing, a semiconductor chip and a conductive trace, wherein the insulative housing includes a top surface, a bottom surface, and a peripheral side surface between the top and bottom surfaces, the chip includes a conductive pad, the conductive trace includes a routing line, a terminal and a lead, the terminal protrudes downwardly from and extends through the bottom surface and is electrically connected to the pad, the lead protrudes laterally from and extends through the side surface and is electrically connected to the pad, the terminal and the lead are spaced and separated from one another outside the insulative housing, and the terminal and the lead are electrically connected to one another by the routing line inside the insulative housing and outside the chip.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor package device, comprising: an insulative housing with a top surface, a bottom surface, and a peripheral side surface between the top and bottom surfaces, wherein the insulative housing includes a first single-piece housing portion and a second single-piece housing portion; a semiconductor chip within the insulative housing, wherein the chip includes an upper surface and a lower surface, the upper surface includes a conductive pad, the upper surface faces towards the bottom surface and faces away from the top surface, and the insulative housing covers the lower surface; a routing line within the insulative housing, wherein the routing line is within and outside a periphery of the chip and is electrically connected to the pad; a terminal that protrudes downwardly from and extends through the bottom surface and is spaced from the side surface and is electrically connected to the pad; and a lead that protrudes downwardly from and contacts and is not integral with the routing line within the insulative housing, protrudes laterally from and extends through the side surface, is outside the periphery of the chip, does not overlap the terminal and is electrically connected to the pad, wherein the first single-piece housing portion contacts the lead and is spaced from the terminal, the second single-piece housing portion contacts the first single-piece housing portion and the terminal, the terminal and the lead are spaced and separated from one another outside the insulative housing, and the terminal and the lead are electrically connected to one another by the routing line inside the insulative housing and outside the chip.
2. The device of claim 1 , wherein the first single-piece housing portion provides the top surface, the side surface and a peripheral portion of the bottom surface, and the second single-piece housing portion provides a central portion of the bottom surface within the peripheral portion of the bottom surface.
3. The device of claim 2 , wherein the peripheral portion of the bottom surface is outside the periphery of the chip, and the central portion of the bottom surface is within and outside the periphery of the chip.
4. The device of claim 2 , wherein the peripheral portion of the bottom surface protrudes downwardly from the central portion of the bottom surface.
5. The device of claim 2 , wherein the first single-piece housing portion contacts the lower surface.
6. The device of claim 1 , wherein the routing line is planar.
7. The device of claim 1 , wherein the terminal is within the periphery of the chip.
8. The device of claim 1 , wherein the terminal is the only electrical conductor that extends through the top or bottom surfaces and is electrically connected to the pad.
9. The device of claim 1 , wherein the device includes a plurality of terminals and leads, the chip includes a plurality of pads, each of the terminals are electrically connected to one of the leads and one of the pads inside the insulative housing and outside the chip, the terminals are arranged as an array that protrudes downwardly from and extends through the bottom surface, and the leads are arranged as TSOP leads that protrude laterally from and extend through the side surface and an opposing peripheral side surface of the insulative housing.
10. The device of claim 1 , wherein the device is devoid of wire bonds, TAB leads and solder joints.
11. A semiconductor package device, comprising: an insulative housing with a top surface, a bottom surface, and peripheral side surfaces between the top and bottom surfaces, wherein the bottom surface includes a peripheral portion adjacent to the side surfaces and a recessed central portion within the peripheral portion and spaced from the side surfaces; a semiconductor chip within the insulative housing, wherein the chip includes an upper surface and a lower surface, the upper surface includes a conductive pad, the upper surface faces towards the bottom surface and faces away from the top surface, and the insulative housing contacts the lower surface; a routing line within the insulative housing, wherein the routing line is within and outside a periphery of the chip and is electrically connected to the pad; a terminal that protrudes downwardly from and is adjacent to the routing line within the insulative housing, protrudes downwardly from and extends through the bottom surface, is spaced from the side surfaces and is electrically connected to the pad; and a lead that protrudes downwardly from and contacts and is not integral with the routing line within the insulative housing, protrudes laterally from and extends through one of the side surfaces, is outside the periphery of the chip, does not overlap the terminal and is electrically connected to the pad, wherein the terminal and the lead are spaced and separated from one another outside the insulative housing, and the terminal and the lead are electrically connected to one another by the routing line inside the insulative housing and outside the chip.
12. The device of claim 11 , wherein the insulative housing consists of a first single-piece housing portion that contacts the lower surface and the lead and is spaced from the terminal and a second single-piece housing portion that contacts the first single-piece housing portion and the terminal.
13. The device of claim 12 , wherein the first single-piece housing portion provides the top surface, the side surfaces and the peripheral portion of the bottom surface, and the second single-piece housing portion provides the central portion of the bottom surface.
14. The device of claim 13 , wherein the peripheral portion of the bottom surface is outside the periphery of the chip, and the central portion of the bottom surface is within and outside the periphery of the chip.
15. The device of claim 13 , wherein the first single-piece housing portion is a transfer molded material, and the second single-piece housing portion is not a transfer molded material.
16. The device of claim 11 , wherein the routing line is planar.
17. The device of claim 11 , wherein the terminal is within the periphery of the chip.
18. The device of claim 11 , wherein the terminal is the only electrical conductor that extends through the top or bottom surfaces and is electrically connected to the pad.
19. The device of claim 11 , wherein the device includes a plurality of terminals and leads, the chip includes a plurality of pads, each of the terminals are electrically connected to one of the leads and one of the pads inside the insulative housing and outside the chip, the terminals are arranged as an array that protrudes downwardly from and extends through the central portion of the bottom surface, and the leads are arranged as TSOP leads that protrude laterally from and extend through two of the side surfaces that oppose one another.
20. The device of claim 11 , wherein the device is devoid of wire bonds, TAB leads and solder joints.
21. A semiconductor package device, comprising: an insulative housing with a top surface, a bottom surface, and a peripheral side surface between the top and bottom surfaces; a semiconductor chip within the insulative housing, wherein the chip includes an upper surface and a lower surface, the upper surface includes a conductive pad, the upper surface faces towards the bottom surface and faces away from the top surface, and the insulative housing contacts the lower surface; a routing line within the insulative housing, wherein the routing line is within and outside a periphery of the chip and is electrically connected to the pad; a terminal that protrudes downwardly from and is adjacent to the routing line within the insulative housing, protrudes downwardly from and extends through the bottom surface, is spaced from the side surface and is electrically connected to the pad; and a lead that protrudes downwardly from and contacts and is not integral with the routing line inside the insulative housing, protrudes laterally from and extends through the side surface, is outside the periphery of the chip, does not overlap the terminal and is electrically connected to the pad, wherein the lead includes a recessed portion that contacts and extends into the insulative housing and is spaced from the top and bottom surfaces and does not overlap the chip and a non-recessed portion that contacts and extends outside the insulative housing and is adjacent to the recessed portion and the bottom surface, the terminal and the lead are spaced and separated from one another outside the insulative housing, and the terminal and the lead are electrically connected to one another by the routing line inside the insulative housing and outside the chip.
22. The device of claim 21 , wherein the insulative housing includes a first single-piece housing portion that contacts the lower surface and the lead and is spaced from the terminal and a second single-piece housing portion that contacts the first single-piece housing portion and the terminal.
23. The device of claim 22 , wherein the first single-piece housing portion provides the top surface, the side surface and a peripheral portion of the bottom surface, and the second single-piece housing portion provides a central portion of the bottom surface within the peripheral portion of the bottom surface.
24. The device of claim 23 , wherein the peripheral portion of the bottom surface is outside the periphery of the chip, and the central portion of the bottom surface is within and outside the periphery of the chip.
25. The device of claim 23 , wherein the peripheral portion of the bottom surface protrudes downwardly from the central portion of the bottom surface.
26. The device of claim 21 , wherein the routing line is planar.
27. The device of claim 21 , wherein the terminal is within the periphery of the chip.
28. The device of claim 21 , wherein the terminal is the only electrical conductor that extends through the top or bottom surfaces and is electrically connected to the pad.
29. The device of claim 21 , wherein the device includes a plurality of terminals and leads, the chip includes a plurality of pads, each of the terminals are electrically connected to one of the leads and one of the pads inside the insulative housing and outside the chip, the terminals are arranged as an array that protrudes downwardly from and extends through the bottom surface, and the leads are arranged as TSOP leads that protrude laterally from and extend through the side surface and an opposing peripheral side surface of the insulative housing.
30. The device of claim 21 , wherein the device is devoid of wire bonds, TAB leads and solder joints.
31. A semiconductor package device, comprising: an insulative housing with a top surface, a bottom surface, and a peripheral side surface between the top and bottom surfaces; a semiconductor chip within the insulative housing, wherein the chip includes an upper surface and a lower surface, the upper surface includes a conductive pad, the upper surface faces towards the bottom surface and faces away from the top surface, and the insulative housing contacts the lower surface; a routing line within the insulative housing, wherein the routing line is within and outside a periphery of the chip and overlaps and is electrically connected to the pad; a terminal that protrudes downwardly from and is adjacent to the routing line within the insulative housing, protrudes downwardly from and extends through the bottom surface, is spaced from the side surface and is electrically connected to the pad; and a lead that protrudes downwardly from and contacts and is not integral with the routing line within the insulative housing, protrudes laterally from and extends through the side surface, is outside the periphery of the chip, does not overlap the terminal and is electrically connected to the pad, wherein the terminal and the lead are spaced and separated from one another outside the insulative housing, and the terminal and the lead are electrically connected to one another by the routing line inside the insulative housing and outside the chip.
32. The device of claim 31 , wherein the insulative housing includes a first single-piece housing portion that contacts the lower surface, the routing line and the lead and is spaced from the terminal and a second single-piece housing portion that contacts the first single-piece housing portion, the routing line and the terminal.
33. The device of claim 32 , wherein the first single-piece housing portion provides the top surface, the side surface and a peripheral portion of the bottom surface, and the second single-piece housing portion provides a central portion of the bottom surface within the peripheral portion of the bottom surface.
34. The device of claim 33 , wherein the peripheral portion of the bottom surface is outside the periphery of the chip, and the central portion of the bottom surface is within and outside the periphery of the chip.
35. The device of claim 33 , wherein the peripheral portion of the bottom surface protrudes downwardly from the central portion of the bottom surface.
36. The device of claim 31 , wherein the routing line is planar.
37. The device of claim 31 , wherein the terminal is within the periphery of the chip.
38. The device of claim 31 , wherein the terminal is the only electrical conductor that extends through the top or bottom surfaces and is electrically connected to the pad.
39. The device of claim 31 , wherein the device includes a plurality of terminals and leads, the chip includes a plurality of pads, each of the terminals are electrically connected to one of the leads and one of the pads inside the insulative housing and outside the chip, the terminals are arranged as an array that protrudes downwardly from and extends through the bottom surface, and the leads are arranged as TSOP leads that protrude laterally from and extend through the side surface and an opposing peripheral side surface of the insulative housing.
40. The device of claim 31 , wherein the device is devoid of wire bonds, TAB leads and solder joints.
41. A semiconductor package device, comprising: an insulative housing with a top surface, a bottom surface, and four peripheral side surfaces between the top and bottom surfaces, wherein the bottom surface includes a peripheral portion shaped as a rectangular peripheral ledge adjacent to the side surfaces and a recessed central portion within the peripheral portion and spaced from the side surfaces, and the peripheral portion protrudes downwardly from the central portion; a semiconductor chip within the insulative housing, wherein the chip includes an upper surface and a lower surface, the upper surface includes a conductive pad, the upper surface faces towards the bottom surface and faces away from the top surface, and the insulative housing contacts the lower surface; a routing line within the insulative housing, wherein the routing line is within and outside a periphery of the chip and overlaps and is electrically connected to the pad; a terminal that protrudes downwardly from and is adjacent to the routing line within the insulative housing, protrudes downwardly from and extends through the central portion of the bottom surface, is spaced from the side surfaces and is electrically connected to the pad; and a lead that protrudes downwardly from and contacts and is not integral with the routing line within the insulative housing, protrudes laterally from and extends through one of the side surfaces, is outside the periphery of the chip, does not overlap the terminal and is electrically connected to the pad, wherein the terminal and the lead are spaced and separated from one another outside the insulative housing, and the terminal and the lead are electrically connected to one another by the routing line inside the insulative housing and outside the chip.
42. The device of claim 41 , wherein the insulative housing includes a first single-piece housing portion that contacts the lower surface, the routing line and the lead and is spaced from the terminal and a second single-piece housing portion that contacts the first single-piece housing portion, the routing line and the terminal.
43. The device of claim 42 , wherein the first single-piece housing portion provides the top surface, the side surfaces and the peripheral portion of the bottom surface, and the second single-piece housing portion provides the central portion of the bottom surface.
44. The device of claim 43 , wherein the peripheral portion of the bottom surface is outside the periphery of the chip, and the central portion of the bottom surface is within and outside the periphery of the chip.
45. The device of claim 43 , wherein the first single-piece housing portion is a transfer molded material, and the second single-piece housing portion is not a transfer molded material.
46. The device of claim 41 , wherein the routing line is planar.
47. The device of claim 41 , wherein the terminal is within the periphery of the chip.
48. The device of claim 41 , wherein the terminal is the only electrical conductor that extends through the top or bottom surfaces and is electrically connected to the pad.
49. The device of claim 41 , wherein the device includes a plurality of terminals and leads, the chip includes a plurality of pads, each of the terminals are electrically connected to one of the leads and one of the pads inside the insulative housing and outside the chip, the terminals are arranged as an array that protrudes downwardly from and extends through the central portion of the bottom surface, and the leads are arranged as TSOP leads that protrude laterally from and extend through two of the side surfaces that oppose one another.
50. The device of claim 41 , wherein the device is devoid of wire bonds, TAB leads and solder joints.
51. A semiconductor package device, comprising: an insulative housing with a top surface, a bottom surface, and a peripheral side surface between the top and bottom surfaces; a semiconductor chip within the insulative housing, wherein the chip includes an upper surface and a lower surface, the upper surface includes a conductive pad, the upper surface faces towards the bottom surface and faces away from the top surface, and the insulative housing contacts the lower surface; a routing line within the insulative housing, wherein the routing line is within and outside a periphery of the chip and overlaps and is electrically connected to the pad; a terminal that protrudes downwardly from and is adjacent to the routing line within the insulative housing, protrudes downwardly from and extends through the bottom surface, is spaced from the side surface and is electrically connected to the pad; and a lead that protrudes downwardly from and contacts and is not integral with the routing line within the insulative housing, protrudes laterally from and extends through the side surface, is outside the periphery of the chip, does not overlap the terminal and is electrically connected to the pad, wherein the lead includes a recessed portion that extends into the insulative housing and is spaced from the top and bottom surfaces and a non-recessed portion that extends outside the insulative housing and is adjacent to the recessed portion and contacts the insulative housing, the recessed and non-recessed portions each include four outer surfaces, three of the outer surfaces of the recessed and non-recessed portions that do not face in the same direction as the bottom surface are coplanar with one another where the recessed and non-recessed portions are adjacent to one another, one of the outer surfaces of the recessed and non-recessed portions that face in the same direction as the bottom surface are not coplanar with one another where the recessed and non-recessed portions are adjacent to one another, the terminal and the lead are spaced and separated from one another outside the insulative housing, and the terminal and the lead are electrically connected to one another by the routing line inside the insulative housing and outside the chip.
52. The device of claim 51 , wherein the insulative housing includes a first single-piece housing portion that contacts the lower surface and the lead and is spaced from the terminal and a second single-piece housing portion that contacts the first single-piece housing portion and the terminal.
53. The device of claim 52 , wherein the first single-piece housing portion provides the top surface, the side surface and a peripheral portion of the bottom surface, and the second single-piece housing portion provides a central portion of the bottom surface within the peripheral portion of the bottom surface.
54. The device of claim 53 , wherein the peripheral portion of the bottom surface is outside the periphery of the chip, and the central portion of the bottom surface is within and outside the periphery of the chip.
55. The device of claim 53 , wherein the peripheral portion of the bottom surface protrudes downwardly from the central portion of the bottom surface.
56. The device of claim 51 , wherein the routing line is planar.
57. The device of claim 51 , wherein the terminal is within the periphery of the chip.
58. The device of claim 51 , wherein the terminal is the only electrical conductor that extends through the top or bottom surfaces and is electrically connected to the pad.
59. The device of claim 51 , wherein the device includes a plurality of terminals and leads, the chip includes a plurality of pads, each of the terminals are electrically connected to one of the leads and one of the pads inside the insulative housing and outside the chip, the terminals are arranged as an array that protrudes downwardly from and extends through the bottom surface, and the leads are arranged as TSOP leads that protrude laterally from and extend through the side surface and an opposing peripheral side surface of the insulative housing.
60. The device of claim 51 , wherein the device is devoid of wire bonds, TAB leads and solder joints.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 2, 2003
January 24, 2006
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