Low voltage sense amplifier for operation under a reduced bit line bias voltage

1. A low voltage sense amplifier device in a flash memory, the device comprising: a regulated low voltage charge pump to produce a substantially fixed charge pump voltage in response to a range of supply voltages; a sense amplifier circuit coupled to the regulated low voltage charge pump and powered by the charge pump voltage, for generating differential voltages in response to a sensed current on a bit line of the flash memory and a chip enable signal for the flash memory; and a differential amplifier circuit, coupled to and powered by the charge pump voltage, for generating a logical output signal in response to the differential voltages.

2. The device of claim 1 wherein the charge pump voltage is 1.8V for the range of the supply voltages of 1.35 to 2.20V.

3. The device of claim 1 wherein the sense amplifier circuit is comprised of a plurality of transistors that are powered by the range of supply voltages.

4. The device of claim 1 wherein the sense amplifier circuit comprises a current reference circuit to generate a reference current for the sense amplifier circuit.

5. The device of claim 1 wherein the logical output signal indicates a programmed state of a memory cell coupled to the bit line.

6. The device of claim 5 wherein a bit line bias to the memory cell is less than 0.8 V.

7. A low voltage sense amplifier device in a flash memory, the device comprising: a regulated low voltage charge pump that generates a regulated voltage in response to a clock signal and an enable signal; a sense amplifier circuit, powered by the regulated voltage, for generating differential voltages in response to a chip enable signal to the flash memory and a sensed current on a bit line coupled to a first memory cell, the sense amplifier circuit having a sense circuit and a reference circuit; and a differential amplifier circuit, powered by the regulated voltage, for generating a logical output signal in response to the differential voltages, the logical output indicating a programmed state of the first memory cell.

8. The device of claim 7 wherein the clock signal and the enable signal of the regulated low voltage charge pump are input to a first and second plurality of delay gates to generate a plurality of delayed clock signals and a plurality of delayed enable signals.

9. The device of claim 8 wherein the first and second current reference circuits are powered by a voltage source that is different from the regulated low voltage charge pump.

10. The device of claim 7 wherein the sense circuit and the reference circuit are equalized by an equalization circuit in response to an equalization signal.

11. The device of claim 10 wherein the equalization circuit is comprised of a transistor and the equalization signal is generated in response to at least one of the chip enable signal or a change in state of address lines to the flash memory.

12. A memory device comprising: a flash memory array having a plurality of bit lines coupled to a plurality of memory cells, the memory array coupled to a first supply voltage, a clock signal, a plurality of address lines, and a chip enable signal; a regulated low voltage charge pump that generates a fixed second supply voltage in response to and range of supply voltages, the clock signal, and the chip enable signal; a sense amplifier circuit comprising a sense circuit and a reference circuit that are equalized by an equalization circuit in response to one of the chip enable signal or a state change of the plurality of address lines, the sense amplifier circuit powered by the second supply voltage and generating differential voltages in response to a sensed current on at least one bit line of the plurality of bit lines; and a differential amplifier circuit, powered by the second supply voltage, for generating a logical output signal in response to the differential voltages.

13. The memory device of claim 12 wherein the sensed current varies in response to a programmed state of a read memory cell.

14. The memory device of claim 12 and further comprising a precharge circuit that precharges a bit line prior to a read operation of a memory cell coupled to the bit line.

15. A method for operating a sense amplifier device coupled to a flash memory array to provide nominal bit line biasing of flash memory cells in the flash memory array, the method comprising: providing a regulated voltage to a sense amplifier circuit, comprising a sense circuit and a reference circuit, that is coupled to memory array bit lines in response to a range of supply voltages, a clock signal, a plurality of address lines, and a chip enable signal; equalizing the sense circuit and the reference circuit; providing the regulated voltage to a differential amplifier circuit; the sense amplifier circuit generating differential voltages in response to sensed current on the memory array bit lines; and the differential amplifier circuit generating a logical one or a logical zero signal in response to the differential voltages.

16. The method of claim 15 and further including generating a separate current reference, each from a different current reference circuit, for a sense circuit and a reference circuit of the sense amplifier circuit.

17. The method of claim 15 and further including maintaining the nominal bit line biasing as the supply voltage either increases or decreases.

18. The method of claim 17 wherein the equalizing is performed in response to the chip enable signal.

19. The method of claim 17 wherein the equalizing is performed in response to a change in state of the plurality of address lines.