A method for providing a current path during switching transitions of a switching circuit while limiting the short circuit current. In one embodiment, a switching circuit includes a passive break-before-make element in series with two switches. An alternate embodiment includes a make-before-break element in parallel with the switches. The passive break-before-make element, or make-before-break element, provides a high impedance in a short term and a low impedance in a long term. The switching circuit may be coupled to a load through a low pass filter. In one embodiment, the switching circuit is used in a switching audio amplifier circuit, where correction of nonlinearities incorporates analog feedback to modify the duty ratio of a digitally generated switching signal in the analog domain.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A switching circuit having feedback, comprising: a differentia 1 duty ratio adjuster (DDRA) having a first input to receive a pulse width modulation (PWM) signal, a second input to receive a reference voltage, and a third input to receive a first feedback signal, wherein the DDRA comprises: a first digital gate having a first input to receive the PWM signal; a first duty ratio modulator having a first input to receive the PWM signal and a second input to receive the first feedback signal; and a second digital gate having a first input to receive an output of the first duty ratio modulator.
2. The switching circuit of claim 1 , further comprising an error amplifier coupled to the DDRA and having a first output to provide the first feedback signal to the DDRA.
3. The switching circuit of claim 2 , wherein the first duty ratio modulator further comprises a first resistor, a second resistor, and a capacitor.
4. The switching circuit of claim 3 , wherein: a first terminal of the first resistor is coupled to the first feedback signal, and a second terminal of the first resistor is coupled to a first terminal of the second resistor and a first terminal of the capacitor; a second terminal of the second resistor is coupled to receive the PWM signal; and a second terminal of the capacitor is coupled ground.
5. The switching circuit of claim 3 , wherein the second resistor and capacitor slows down edge transitions of the PWM signal and introduces a time delay into the PWM signal.
6. The switching circuit of claim 5 , wherein the first digital gate converts the output of the first duty ratio modulator to a digital signal.
7. The switching circuit of claim 2 , further comprising: a power stage having an input to receive an output of the second digital gate; and a summing node having a first input to receive an output of the power stage and a second input to receive an output of the first digital gate, wherein the summing node provides a difference to the error amplifier.
8. The switching circuit of claim 7 , wherein the DDRA further comprises a second duty ratio modulator having a first input to receive the PWM signal, and coupled to provide an output to the first input of the first digital gate, wherein the first duty ratio modulator introduces a delay, and the second duty ratio modulator compensates for the delay.
9. The switching circuit of claim 8 , wherein the second duty ratio modulator includes a second input to receive a second feedback signal.
10. The switching circuit of claim 8 , wherein the second duty ratio modulator includes a second input coupled to ground.
11. The switching circuit of claim 8 , wherein the first duty ratio modulator and the second duty ratio modulator each further comprise a first resistor, a second resistor, and a capacitor, wherein: the second resistor and capacitor of the first duty ratio modulator introduces a time delay into the PWM signal, and the second resistor and capacitor of the second duty ratio modulator compensates for the time delay.
12. The switching circuit of claim 11 , wherein second resistor and capacitor of the second duty ratio modulator further compensates for a time delay of the power stage.
13. The switching circuit of claim 8 , further comprising: a third digital gate having a first input to receive the PWM signal, a second input to receive the reference voltage, and an output coupled to the second duty ratio modulator and the first duty ratio modulator, wherein the third digital gate removes noise from the PWM signal.
14. The switching circuit of claim 9 , wherein the error amplifier includes a second output to provide the second feedback signal to the second duty ratio modulator.
15. The switching circuit of claim 1 , wherein the switching circuit is internal to an integrated circuit.
16. The switching circuit of claim 1 , wherein: the first digital gate has a second input to receive the reference voltage; and the second digital gate has a second input to receive the reference voltage.
17. A method of providing feedback to a switching circuit having a power stage, comprising: receiving a PWM signal; adjusting the PWM signal to form a lower noise PWM signal; modulating the PWM signal using feedback to form a corrected PWM signal; providing the corrected PWM signal to the power stage to produce an amplified PWM signal; and producing a feedback signal based at least in part on the amplified PWM signal and the lower noise PWM signal.
18. The method of claim 17 , wherein modulating the PWM signal comprises selectively modifying a duty ratio corresponding to the PWM signal based at least in part on the feedback signal.
19. The method of claim 18 , wherein modulating further comprises delaying the PWM signal.
20. The method of claim 19 , wherein modulating the PWM signal uses at least two resistors and at least one capacitor.
21. The method of claim 19 , wherein adjusting the PWM signal comprises delaying the PWM signal.
22. The method of claim 21 , wherein delaying the PWM signal to form the lower noise PWM signal is performed to reduce the feedback signal.
23. The method of claim 17 , wherein producing the feedback signal comprises calculating a difference between the lower noise PWM signal and the amplified PWM signal.
24. A switching circuit having feedback, comprising: a differential duty ratio adjuster (DDRA) having a first input to receive a pulse width modulation (PWM) signal, a second input to receive a reference voltage, and a third input to receive a first feedback signal, wherein the DDRA comprises: a first combinational logic circuit having an input for receiving the PWM signal and an output for providing a delayed PWM signal; and a second combinational logic circuit having a first input for receiving the PWM signal, a second input for receiving a feedback signal, and an output for providing a modulated PWM signal, wherein the modulated PWM signal is modulated in response to the feedback signal.
25. The switching circuit of claim 24 , wherein: the second combinational logic circuit further comprises a first delay line having a first input to receive the PWM signal and coupled to provide a delay in the modulated PWM signal; and the first combinational logic circuit comprises a second delay line having a first input to receive the PWM signal, wherein the second delay line provides a delay in the delayed PWM signal that is approximately equal to the delay in the modulated PWM signal.
26. The switching circuit of claim 25 , wherein: the second combinational logic circuit comprises a first latch coupled to the first delay line and having an output to provide the modulated PWM signal; and the first combinational logic circuit comprises a second latch coupled to the second delay line and having an output to provide the delayed PWM signal.
27. The method of claim 25 , wherein the first delay line includes a second input based at least in part on the feedback signal, wherein the feedback signal selectively modifies a duty ratio of the PWM signal to produce the modulated PWM signal.
28. The method of claim 27 , wherein the second input is further based in part on a reference voltage, wherein the reference voltage is used in part to determine the delay of the modulated PWM signal.
29. The method of claim 28 , wherein the second delay line includes a second input for receiving the reference voltage, wherein the reference voltage is used in part to determine the delay of the delayed PWM signal.
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April 20, 2004
February 7, 2006
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