Intermediate substrate

1. An intermediate substrate comprising: a substrate core comprising a main core body portion constructed of a sheet of polymer material and including a subsidiary core accommodation portion opening at a first main surface of the main core body portion as to reduce the overall transverse thickness thereof n the region of said subsidiary core accommodation portion, and a ceramic subsidiary core portion, accommodated in said subsidiary core accommodation portion and of a thickness which, together with the transverse thickness of any remaining portion of said main core body portion in said region, matches the overall transverse thickness of said main core body portion; a first terminal array formed on a first main surface side of said substrate core and comprising first side first terminals and first side second terminals some of which function as power terminals and others of which function as ground terminals, said first terminal array further comprising first side signal terminals; and a second terminal array formed on a second main surface side of said substrate core and comprising second side first terminals and second side second terminals which are conductively connected to said first side first terminals and said first side second terminals, respectively, and second side signal terminals conductively connected to said first side signal terminals; said ceramic subsidiary core portion comprising a substantially planar base body and a multilayered thin film capacitor portion formed on the first main surface side of the base body and comprising a first conductive thin film electrode and a second conductive thin film electrode separated from said first electrode by a thin film dielectric layer so as to prevent direct current flow between said electrodes, said first side first terminals and said first side second terminals of said first terminal array being conductively connected to said first electrode and said second electrode, respectively, such that direct current flow between said first side first terminals and said first side second terminals is prevented.

2. The intermediate substrate according to claim 1 wherein on the first main surface side of said thin film capacitor portion, said first side first terminals and said first side second terminals each comprise a plurality of terminals disposed at a predetermined interval, and the first side first terminals and the first side second terminals are electrically coupled to said first thin film electrode and said second thin film electrode, respectively, located nearest to said first main surface, either directly or through auxiliary coupling conductor portions.

3. The intermediate substrate according to claim 1 wherein said dielectric thin film layer is constructed of a high dielectric constant ceramic.

4. The intermediate substrate according to claim 3 wherein said base body is thicker than said thin film capacitor portion and comprises a ceramic material having a lower linear expansion coefficient than said high dielectric constant ceramic.

5. The intermediate substrate according to claim 4 wherein said base body comprises a ceramic material having a higher Young's modulus than said high dielectric constant ceramic.

6. The intermediate substrate according to claim 1 wherein said base body comprises a layered ceramic capacitor base body comprising alternate layers comprising at least one baked ceramic dielectric layer and at least one electrode conductor layer baked together with the baked ceramic dielectric layer.

7. The intermediate substrate according to claim 1 wherein said first terminal array is formed at a position at which, when said first terminal array is geometrically projected orthogonally to a reference plane parallel to a planar face of said substrate core, a resultant projection image of said first terminal array is entirely included in a corresponding geometrically projected area of said ceramic subsidiary core portion.

8. The intermediate substrate according to claim 7 wherein said ceramic subsidiary core portion is of an area at least equal to a corresponding area encompassed by said first terminal array.

9. The intermediate substrate according to claim 1 wherein, in said substrate core, the first main surface of said ceramic subsidiary core portion and the first main surface of said main core body portion are covered by a first wiring layer portion comprising alternate layers comprising a dielectric layer comprised of a polymer material and a conductive layer including a surface conductor for serving a wiring, ground or power supply function, and wherein said first terminal array is exposed on a first main surface of the first wiring layer portion.

10. The intermediate substrate according to claim 9 wherein a first side first surface conductor and a first side second surface conductor, which are respectively conductively connected to said first side first terminals and first side second terminals of said first terminal array, cover the first main surface of said main core body portion, together with said ceramic subsidiary core portion, within said first wiring layer portion; and a first side first surface conductor and a first side second surface conductor are conductively connected, respectively, to a first through hole conductor and a second through hole conductor each of which extends transversely of said main core body portion so as to bypass said ceramic subsidiary core portion.

11. The intermediate substrate according to claim 8 wherein, in said first terminal array, said first side first terminals and first side second terminals are disposed within an inside array area and said first side signal terminals are disposed within an outside array area, wherein said substrate further comprises a first side signal wiring, which provides a signal transmission path outside of said ceramic subsidiary core portion, is disposed within said first wiring layer portion so as to be conductively connected to said first side signal terminals, and wherein a terminal end of the first side signal wiring is conductively connected to a signal through hole conductor which extends transversely of said main core body portion and which bypasses said ceramic subsidiary core portion.

12. The intermediate substrate according to claim 11 wherein said first thin film electrode and said second thin film electrode of said thin film capacitor portion are disposed inwardly of said first side signal terminals.

13. The intermediate substrate according to claim 9 wherein a first subsidiary core conductor and a second subsidiary core conductor, which respectively correspond to said first side first terminals and first side second terminals of said first terminal array and which are respectively conductively connected to said second side first terminals and second side second terminals of said second terminal array, extend transversely of said ceramic subsidiary core portion, and the first subsidiary core conductor and the second subsidiary core conductor are conductively connected to said first side first terminals and first side second terminals through via conductors extending through each said dielectric layer of said first wiring layer portion.

14. The intermediate substrate according to claim 1 wherein said first side first terminals and said first side second terminals, which constitute said first terminal array, are exposed on the first main surface of said ceramic subsidiary core portion and a first subsidiary core conductor and a second subsidiary core conductor, which correspond to said first side first terminals and first side second terminals of said first terminal array and are conductively connected to said second side first terminals and second side second terminals of said second terminal array, extend transversely of the ceramic subsidiary core portion.

15. The intermediate substrate according to claim 14 wherein said first side signal terminals, which constitute said first terminal array, are exposed on the first main surface of said ceramic subsidiary core portion, and a signal subsidiary core conductor, which corresponds to the first side signal terminals and is conductively connected to said second side signal terminals of said second terminal array, extends transversely of the ceramic subsidiary core portion.

16. The intermediate substrate according to claim 14 wherein, outside of said ceramic subsidiary core portion, only the first main surface of said main core body portion is covered with a first wiring layer portion comprising alternate laminated layers comprising at least one dielectric layer comprised of polymer material and at least one conductive layer containing a surface conductor for serving a wiring, ground or supply power function, and said first side signal terminals are exposed on the surface of said first wiring layer portion, and a first side signal wiring, which provides a signal transmission path outside of said ceramic subsidiary core portion, is disposed within said first wiring layer portion so as to be conductively connected to said first side signal terminals, and a terminal end of the first side signal wiring is conductively connected to a signal through hole conductor which extends transversely of said main core body portion and which bypasses said ceramic subsidiary core portion.

17. An intermediate substrate comprising: a substrate core comprising a main core body portion constructed of a sheet of polymer material and including a subsidiary core accommodation portion opening at a first main surface of the main core body portion so as to reduce the overall transverse thickness thereof in the region of said subsidiary core accommodation portion, and a subsidiary core portion, constructed of a material having a smaller linear expansion coefficient than said main core body portion, accommodated in said subsidiary core accommodation portion and having a thickness which, together with the transverse thickness of any remaining portion of said main core body portion in said region, matches the overall transverse thickness of said main core body portion; a first terminal array formed on a first main surface side of said substrate core and comprising first side first terminals and first side second terminals some of which function as power terminals and others of which function as ground terminals, said first terminal array further comprising first side signal terminals; and a second terminal array formed on a second main surface side of said substrate core and comprising second side first terminals and second side second terminals which are conductively connected to said first side first terminals and said first side second terminals, respectively, and second side signal terminals conductively connected to said first side signal terminals; said first terminal array being disposed at a position overlapping a resultant projected area of said subsidiary core portion produced by geometric projection of said subsidiary core portion orthogonally onto a reference plane parallel to a planar face of said substrate core, and said intermediate substrate further comprising, accommodated in said subsidiary core portion, a multilayered capacitor, comprising, in order, a first conductive electrode layer, a dielectric layer and a second conductive electrode layer, and conductively connected to said first side second terminals and said second side second terminals.

18. The intermediate substrate according to claim 17 wherein, in said substrate core, the first main surface of said subsidiary core portion, and the first main surface of said main core body portion are covered with a first wiring layer portion comprising alternate layers comprising at least one dielectric layer comprised of polymer material and at least one conductive layer including a surface conductor functioning as wiring, ground or power supply conductors, and said first terminal array is exposed on the first main surface of the first wiring layer portion.

19. The intermediate substrate according to claim 18 wherein a first subsidiary core conductor and a second subsidiary core conductor, corresponding to said first side first terminals and first side second terminals of said first terminal array and conductively connected to said second side first terminals and second side second terminals of said second terminal array, extend transversely of said subsidiary core portion, the first subsidiary core conductor and the second subsidiary core conductor being conductively connected to said first side first terminals and first side second terminals through via conductors penetrating through the at least one dielectric layer of said first wiring layer portion.

20. The intermediate substrate according to claim 18 wherein, in said first terminal array, said first side first terminals and first side second terminals are disposed within an inside array area and said first side signal terminals are disposed within an outside array area, and wherein a first side signal wiring, which provides a signal transmission path outside of said subsidiary core portion, is disposed within said first wiring layer portion so as to be conductively connected to said first side signal terminals, and a terminal end of the first side signal wiring is conductively connected to a signal through hole conductor which extends transversely of said main core body portion and which bypasses said subsidiary core portion.

21. The intermediate substrate according to claim 17 wherein said first side first terminals and said first side second terminals, which constitute said first terminal array, are exposed on the first main surface of said subsidiary core portion and a first subsidiary core conductor and a second subsidiary core conductor, which correspond to said first side first terminals and said first side second terminals of said first terminal array and are conductively connected to said second side first terminals and second side second terminals of said second terminal array, extend transversely of the core portion.

22. The intermediate substrate according to claim 21 wherein an outer peripheral portion of the first main surface of said subsidiary core portion has disposed thereon a first wiring layer portion comprising alternating layers comprising at least one dielectric layer comprised of a polymer material and at least one conductive layer containing a surface conductor for serving a wiring, ground or power supply function, together with the first main surface of said core main body portion, and said first side signal terminals are exposed on the surface of said first wiring layer portion, and wherein a first side signal wiring, which provides a signal transmission path outside of the subsidiary core portion, is disposed within said first wiring layer portion and is conductively connected to said first side signal terminals, and a terminal end of the first side signal wiring is conductively connected to a signal through hole conductor which extends transversely of said main core body portion and which bypasses said subsidiary core portion.

23. An intermediate substrate comprising: a substrate core comprising a main core body portion constructed of a sheet of polymer material and including subsidiary core accommodation portion opening at a first main surface of the main core body portion so as to reduce the overall transverse thickness thereof in the region of said subsidiary core accommodation portion, and a subsidiary core portion, constructed of material having a coefficient of linear expansion smaller than that of said main core body portion, accommodated in said subsidiary core accommodation portion and of a thickness which, together with the transverse thickness of any remaining portion of said main core body portion in said region, matches the overall transverse thickness of said main core body portion; a first terminal array formed on a first main surface of said substrate core and comprising first side first terminals and first side second terminals functioning as power terminals and ground terminals, respectively, and first side signal terminals; and a second terminal array formed on a second main surface of said substrate core and comprising second side first terminals and second side second terminals, conductively connected to said first side first terminals and said first side second terminals, and second side signal terminals conductively connected to said first side signal terminals; said first terminal array being positioned entirely within a projected area of said subsidiary core portion geometrically projected orthogonally into a reference plane parallel to a planar face of said substrate core and said substrate further comprising a multilayered capacitor, comprising first and second conductive electrode layers separated by a dielectric layer, conductively connected to said first side second terminal and said second side second terminals and accommodated in said subsidiary core accommodation portion.