An integrated circuit memory device has an array of memory cells arranged in a plurality of rows and columns and a plurality of row lines and a plurality of column lines. Cells arranged in the same row are connected by a common row line, and cells arranged in the same column are connected by a common column line. Each cell in the array is addressed by an address signal which has a plurality of bits. A sense amplifier circuit is connectable to one or more of the plurality of column lines of the array. An address input terminal receives in series the plurality of bits of the address signal. Each of the column lines is connectable to a pre-charge voltage, in response to a read command. A decoder circuit receives the address signal and decodes the address signal as each of the plurality of bits is received and disconnects certain of the column lines to the pre-charge voltage in response to the decoding, and activates the sense amplifier circuit after all of the plurality of bits of the address signal are received.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An integrated circuit memory device comprising: an array of memory cells arranged in a plurality of rows and columns having a plurality of row lines and a plurality of column lines, with cells arranged in the same row connected by a common row line, and cells arranged in the same column connected by a common column line; wherein each cell in said array being addressed by an address signal having a plurality of bits; a sense amplifier circuit connectable to one or more of said plurality of column lines of said array; an address input terminal for receiving said plurality of bits of said address signal in series; each of said column lines connectable to a first voltage; and a decoder circuit for receiving said address signal and for decoding said address signal as each of said plurality of bits is received and for disconnecting certain of said column lines to said first voltage in response to said decoding; and for activating said sense amplifier circuit after all of said plurality of bits of said address signal are received.
2. The memory device of claim 1 wherein each of said cells is a non-volatile memory cell.
3. The memory device of claim 2 wherein each of said non volatile memory cells is a stacked gate floating gate non-volatile memory cell.
4. The memory device of claim 2 wherein each of said non volatile memory cells is a split gate floating gate non-volatile memory cell having a first region in a semiconductor substrate, a second region in said semiconductor substrate spaced apart from said first region by a channel region; a floating gate for controlling the conduction of current in a first portion of said channel region; a control gate for controlling the conduction of current in a second portion of said channel region; wherein said control gate is separated from said floating gate by an insulator permitting the Fowler Nordheim tunneling of electrons from said floating gate to said control gate.
5. The memory device of claim 1 further comprising a shift register; said shift register for receiving said plurality of bits of said address signal.
6. The memory device of claim 5 further comprising a row decoder for receiving a first portion of said plurality of bits of said address signal and for decoding said first portion and for selecting a row line in response thereto.
7. The memory device of claim 6 wherein said decoder circuit is a column decoder for receiving a second portion of said plurality of bits of said address signal and for decoding said second portion and for selecting a column line in response thereto.
8. The memory device of claim 1 further comprising a multiplexer, and wherein said sense amplifier circuit is connectable to said plurality of column lines through said multiplexer.
9. The memory device of claim 1 further comprising a plurality of switches, each interposed between a column line and said first voltage; wherein each of said switches is responsive to the output of said decoder circuit.
10. The memory device of claim 1 wherein each of said column lines is connectable to the first voltage in response to a read command, thereby initiating a pre-charging sequence.
11. The memory device of claim 1 wherein said address signal having a row address portion and a column address portion, wherein each of said row address portion and column address portion comprising a plurality of bits.
12. The memory device of claim 11 wherein each of said column lines is connectable to the first voltage in response to the first bit of said column address portion.
13. A method of operating an integrated circuit memory device, having an array of memory cells arranged in a plurality of rows and columns, with a plurality of row lines and a plurality of column lines, with memory cells in the same row connected by a common row line, and memory cells in the same column connected by a common column line, wherein each cell in said array being addressed by an address signal having a plurality of bits; said memory device further having a sense amplifier circuit connectable to at least one of said plurality of column lines, said method comprising: receiving said plurality of bits of said address signal in series; pre-charging said plurality of column lines of said array; selectively deactivating the pre-charging of another plurality of column lines of said array, wherein said another plurality of column lines are unselected column lines; activating said sense amplifier circuit for detecting the state of said addressed cell after all of said plurality of bits of said address signal are received.
14. The method of claim 13 further comprising: activating said sense amplifier circuit at least one clock cycle after pre-charging said plurality of column lines of said array.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 19, 2004
March 7, 2006
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