Patentable/Patents/US-7010271
US-7010271

Circuits and methods for reducing interference from switched mode circuits

PublishedMarch 7, 2006
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A system 100 including a radio receiver 101/108 and switched mode circuitry 114/115 operating at a selected switching frequency is disclosed. Circuitry 207–209 sets the switching-circuitry of the switched mode circuitry 114/115 as a function of a frequency of a signal being received by a radio receiver 101/108.

Patent Claims
11 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A system comprising: an AM radio receiver; switched mode circuitry comprising an audio amplifier for driving an audio channel of said radio receiver and operating at a selected switching frequency, the audio amplifier including pulse width modulation circuitry operating in response to a clock signal of a selected frequency and another clock signal having a frequency of a selected frequency divide ratio to the frequency of the clock signal, the pulse width modulation circuitry outputting a pulse width modulated signal at said selected switching frequency and changing operating characteristics in response to a change in said divide ratio including changing a zero point of the pulse of the pulse width modulated signal; and circuitry for setting said switching frequency of said switched mode circuitry by setting said divide ratio as a function of a frequency of an AM signal being received by said radio receiver.

2

2. The system of claim 1 wherein said switched mode circuitry comprises a Class D amplifier.

3

3. The system of claim 1 wherein said circuitry for setting said switching frequency of said switched mode circuitry comprises: a plurality of crystals of differing resonance frequencies; a crystal oscillator for generating said switching frequency from a selected one of said crystals; and control circuitry for selecting said selected one of said crystals a to set the frequency of said clock signal.

4

4. The system of claim 1 wherein said circuitry for setting said switching frequency of said switched mode circuitry comprises: a signal generator for generating a base frequency of the clock signal; a programmable divider for dividing said base frequency by a selected divisor to generate said another clock signal of a frequency with said selected divide ratio to the base frequency of the clock signal; and control circuitry for selecting said divisor.

5

5. The system of claim 1 wherein said circuitry for setting said switching frequency includes a microcontroller operable to select said switching frequency in response to selection of a reception frequency band by user input.

6

6. The system of claim 1 wherein said circuitry for setting said switching frequency detects said frequency of said signal received by said radio receiver by measuring a local oscillator frequency.

7

7. The system of claim 1 wherein said switching frequency is selected such that at least one harmonic of said switching frequency lies outside a frequency band including said signal being received by said radio receiver.

8

8. The system of claim 1 wherein said circuitry for setting said switching frequency is operable to set said switching frequency to a selected one of a set of frequency steps differing in frequency by at least two percent.

9

9. A system comprising: an radio receiver; an audio amplifier for driving an audio channel of said redio receiver and operating at a switching frequency, the audio amplifier including pulse width modulation circuitry operating in response to a clock signal and another clock signal of a frequency of selected divide ratio to the frequency of the clock signal and outputting a pulse width modulated signal at the switching frequency, a change in the divide ratio changing operating characteristics of the pulse width modulation circuitry including varying distortion correction operations in response to a change in the divide ratio and the switching frequency; and circuitry for setting said switching frequency by changing the divide ratio including a divider for dividing the frequency of the clock signal to generate the freguency of the another clock signal of the selected divide ratio.

10

10. The system of claim 9 , wherein the radio receiver comprises an AM radio receiver.

11

11. The system of claim 9 , wherein the pulse width modulation circuity changes a pulse width of the pulse width modulated signal in response to a change in the divide ratio.

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Patent Metadata

Filing Date

November 18, 2003

Publication Date

March 7, 2006

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Cite as: Patentable. “Circuits and methods for reducing interference from switched mode circuits” (US-7010271). https://patentable.app/patents/US-7010271

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