Patentable/Patents/US-7015121
US-7015121

Semiconductor device and method of manufacturing the same

PublishedMarch 21, 2006
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A method of manufacturing a semiconductor device comprises a step of depositing a crystalline insulating layer oriented in a predetermined crystal face orientation by epitaxial growth on an amorphous semiconductor layer, a step of depositing a second amorphous semiconductor layer on the crystalline insulating layer, a step of growing said first and second semiconductor layers into a polycrystal or single crystal layer in a solid phase, using said crystalline insulating film as core, and a step of forming a functional element containing said first and second semiconductor layer.

Patent Claims
5 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A method of manufacturing a semiconductor device comprising: depositing an amorphous Si layer directly on an insulating substrate containing Si; depositing a crystalline insulating layer oriented in a predetermined crystal face orientation by growing a CeO 2 layer on said amorphous Si layer; forming a polycrystal or single crystal semiconductor substrate by growing said amorphous Si layer in a solid phase, using said crystalline insulating layer of CeO 2 as core; and forming a functional element in said polycrystal or single crystal semiconductor substrate.

2

2. A method according to claim 1 , wherein said insulating substrate is a glass substrate.

3

3. A method according to claim 1 , wherein said insulating substrate is an SiO 2 substrate.

4

4. A method according to claim 1 , wherein said insulating substrate is formed on a polycrystal or single crystal Si substrate.

5

5. A method according to claim 1 , wherein the method further comprises depositing another amorphous Si layer on said crystalline insulating layer of CeO 2 ; and forming a polycrystal or single crystal layer by growing said other amorphous Si layer in a solid phase, using said crystalline insulating layer of CeO 2 as core.

Classification Codes (CPC)

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Patent Metadata

Filing Date

August 4, 2004

Publication Date

March 21, 2006

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