A dual work function semiconductor structure with borderless contact and method of fabricating the same are presented. The structure may include a field effect transistor (FET) having a substantially cap-free gate and a conductive contact to a diffusion adjacent to the cap-free gate, wherein the conductive contact is borderless to the gate. Because the structure is a dual work function structure, the conductive contact is allowed to extend over the cap-free gate without being electrically connected thereto.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor structure comprising a field effect transistor (FET) having a cap-free gate stack and a conductive contact to a diffusion adjacent to said cap-free gate stack, said cap-free gate stack comprising a gate stack without an insulating cap aligned with the gate as part of the gate stack, said cap-free gate stack having a portion of the gate removed from an upper surface thereof to define a notched gate, said conductive contact being isolated from said notched gate by an insulating structure on said notched gate, said insulating structure including an insulating layer disposed within the removed portion of the gate and an insulating sidewall layer on said gate having a height less than or equal to a height of the cap-free gate stack.
2. The structure as recited in claim 1 , wherein said gate comprises an insulating film thin enough so a source/drain implant of the FET penetrates into said gate.
3. The structure as recited in claim 1 , further comprising an implanted source/drain and wherein said implant has a dose in said diffusion, wherein said cap-free gate stack comprises no insulating film capable of blocking more than half said dose.
4. The structure as recited in claim 1 , wherein said conductive contact extends at least partially above said cap-free gate stack without shorting to said gate.
5. The structure as recited in claim 1 , wherein the field effect transistor is a dual work function FET.
6. The structure as recited in claim 1 , wherein the insulating structure further includes an insulating spacer disposed above the insulating layer disposed within the removed portion of the gate.
7. A semiconductor structure comprising a field effect transistor (FET) having a gate stack and a conductive contact to a diffusion adjacent to said gate stack, said gate stack having a portion of the gate removed from an upper surface thereof to define a notched gate, said conductive contact being separated from said notched gate by an insulating structure on said notched gate, said insulating structure including an insulating layer disposed within the removed portion of the gate and an insulating sidewall layer on said gate having a height less than or equal to a height of the gate stack.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 4, 2005
March 21, 2006
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