Isolation device over field in a memory device

1. A memory device comprising: a first memory cell including a first storage node formed in a first substrate region; a second memory cell including a second storage node formed in a second substrate region; an isolation device having an isolation gate responsive to a potential from a power node for preventing conductivity between the first and second storage nodes; and a resistive device coupled between the isolation gate and the power node for reducing current flowing from the power node to a shorted circuit path caused by a defect.

2. The memory device of claim 1 , wherein the isolation device includes a first electrode and a second electrode, wherein the first electrode shares the first substrate region with the first storage node, and wherein the second electrode shares the second substrate region with the second storage node.

3. The memory device of claim 2 , wherein the isolation device further includes a gate dielectric, wherein at least one portion of the gate dielectric is formed in a trench in the substrate.

4. The memory device of claim 1 , wherein the resistive device includes a resistor having a first resistor terminal coupled to the isolation device and a second resistor terminal coupled to the power node.

5. The memory device of claim 1 , wherein the resistive device includes a transistor having a first terminal coupled to the isolation device, a second terminal coupled to the power node, and a gate coupled to a bias node.

6. A memory device comprising: a first storage node for storing a first charge; a second storage node for storing a second charge; an isolation device responsive to a potential from a power node for providing isolation between the first and second storage nodes; and a resistive device coupled in a path between the isolation device and the power node.

7. The memory device of claim 6 further comprising an access transistor for transferring the first charge between the first storage node and a bit line.

8. The memory device of claim 7 further comprising a second access transistor for transferring the second charge between the second storage node and the bit line.

9. The memory device of claim 8 further comprising a first word line for providing a voltage to a gate of the access transistor, and a second word line for providing a voltage to a gate of the second access transistor.

10. The memory device of claim 9 further including a cell plate, wherein the cell plate combines with first storage node for forming a first capacitor, and wherein the cell plate combines with the second storage node for forming a second capacitor.

11. The memory device of claim 6 , wherein the resistive device includes a resistor having a first resistor terminal coupled to the isolation device and a second resistor terminal coupled to the power node.

12. The memory device of claim 6 , wherein the resistive device includes a transistor having a first terminal coupled to the isolation device, a second terminal coupled to the power node, and a gate coupled to a bias node.

13. A memory device comprising: a first capacitor having a capacitor plate, and a first access transistor for transferring a charge between the capacitor plate and a bit line; a second capacitor having a capacitor plate, and second access transistor for transferring a charge between the capacitor plate of the second capacitor and the bit line; an isolation device having a first electrode coupled to the capacitor plate of the first capacitor, a second electrode coupled to the capacitor plate of the second capacitor, and an isolation gate responsive to a voltage from a power node to prevent conductivity between the first and second electrodes; and a resistive device coupled in a path between the isolation gate and the power node.

14. The memory device of claim 13 , wherein the isolation device further includes a gate dielectric between the first and second electrodes, wherein the gate dielectric has a thickness greater than a thickness of a transistor gate dielectric of each of the first and second access transistors.

15. The memory device of claim 13 , wherein the resistive device includes a resistor having a first resistor terminal coupled to the isolation gate and a second resistor terminal coupled to the power node.

16. The memory device of claim 13 , wherein the resistive device includes a transistor having a first terminal coupled to the isolation gate, a second terminal coupled to the power node, and a gate coupled to a bias node.

17. A memory device comprising: a substrate including a first doped region, a second doped region, a third doped region, and a fourth doped region; a first access transistor including a gate, a first terminal formed by the first doped region, and a second terminal formed by the second doped region; a second access transistor including a gate, a first terminal formed by the third doped region, and a second terminal formed by the fourth doped region; a first capacitor including a capacitor plate formed by the second doped region; a second capacitor including a capacitor plate formed by the third doped region; an isolation device including an isolation gate for receiving a potential from a power node, a first electrode formed by the second doped region, a second electrode formed by the third doped region; and a resistive device coupled between the isolation gate and the power node.

18. The memory device of claim 17 , wherein the isolation device has a threshold voltage greater than a supply voltage of the memory device.

19. The memory device of claim 17 , wherein the isolation device includes a gate dielectric having a thickness greater than a thickness of a gate dielectric of each of the first and second access transistors.

20. The memory device of claim 17 , wherein the isolation device includes a gate dielectric, wherein at least a portion of the gate dielectric of the isolation device is formed in a trench in the substrate.

21. The memory device of claim 17 , wherein the isolation device is configured to be inactive during an operation of the memory device.

22. A memory device comprising: a plurality of memory cells arranged in row pairs, each of the row pairs including a first cell row and a second cell row, each memory cell of the first cell row includes a storage node, each memory cell of the second cell row includes a storage node; a plurality of isolation rows, each of the isolation rows including a plurality of isolation devices, each of the isolation devices including an isolation gate responsive to a potential from a power node for providing isolation between the storage node of one of the memory cells in the first cell row and the storage node of one the memory cells of the second cell row; a plurality of isolation lines, each of the isolation lines coupling to the isolation gate of each of the isolation devices within one of the isolation rows, the isolation lines being arranged in M groups, wherein M is an integer, each of the M groups having a group node and multiple isolation lines coupled to the group node; and M current control circuits, each of the M current control circuits coupling between the power node and the group node of one of the M groups.

23. The memory device of claim 22 , wherein each of the M current control circuits is configured to provide a resistance between the power node and a corresponding group node of one of the M groups.

24. The memory device of claim 22 , wherein each of the M current control circuits includes a resistor coupled between the power node and a corresponding group node of one of the M groups.

25. A memory device comprising: a plurality of memory cells arranged in row pairs, each of the row pairs including a first cell row and a second cell row, each memory cell of the first cell row includes a storage node, each memory cell of the second cell row includes a storage node; a plurality of isolation rows, each of the isolation rows including a plurality of isolation devices, each of the isolation devices including an isolation gate responsive to a potential from a power node for providing isolation between the storage node of one of the memory cells in the first cell row and the storage node of one the memory cells of the second cell row; a plurality of isolation lines, each of the isolation lines coupling to the isolation gate of each of the isolation devices within one of the isolation rows, the isolation lines being arranged in M groups, wherein M is an integer, each of the M groups having a group node and having at least one isolation line coupled to the group node; and a plurality of resistive device, each of the resistive device coupling between the power node and the group node of one of the M groups.

26. The memory device of claim 25 , wherein each of the resistive devices is configured to provide a resistance between the power node and a corresponding group node of one of the M groups.

27. The memory device of claim 25 , wherein each of the resistive devices includes a resistor coupled between the power node and a corresponding group node of one of the M groups.

28. A system comprising: a processor; and a memory device coupled to the processor, the memory device including: a first storage node for storing a first data; a second storage node for storing a second data; an transistor coupled between the first and second storage nodes, the isolation device is configured to be responsive to a potential from a power node for providing isolation between the first and second storage nodes; and a resistor coupled in a path between the isolation device and the power.

29. The system of claim 28 , wherein the first and second storage nodes are formed in a substrate of the memory device, and wherein the isolation device includes a gate dielectric, wherein at least a portion of the gate dielectric of the isolation device is formed in a trench between the first and second storage nodes.

30. A method comprising: forming a first storage node; forming a second storage node; forming an isolation device between the first and second storage nodes, the isolation device being configured to be responsive to a potential from a power node for providing isolation between the first and second storage nodes; and forming a resistive device in a path between the isolation device and the power node for controlling a current on the path.

31. The method of claim 30 , wherein the first and second storage nodes are formed in a substrate of the memory device, and wherein the isolation device includes a gate dielectric, wherein at least a portion of the gate dielectric of the isolation device is formed in a trench between the first and second storage nodes.

32. The method of claim 30 , wherein the resistive device includes a resistor.

33. A method comprising: activating a first access transistor to read a charge in a first storage node of a first memory cell of a memory device; activating a second access transistor to read a charge in a second storage node of a second memory cell of the memory device; turning off an isolation device to prevent conductivity between the first and second storage nodes, wherein the isolation device includes a gate responsive to a potential from a power node; and modifying a resistance of a path between the power node and the gate of the isolation device.

34. The method of claim 33 , wherein modifying the resistance includes inserting a resistive device between the power node and the gate of the isolation device.

35. The method of claim 33 , wherein the resistive device includes a resistor.

36. A method comprising: forming an isolation device between a first storage node and a second storage node of a memory device; forming a power node to apply a potential from the power node to a gate of the isolation device to prevent conductivity between the first and second storage nodes; and placing a resistive device between the power node and the gate of the isolation device to reduce current flowing from the power node to a short circuit point caused in by a defect in the memory device.

37. The method of claim 36 , wherein the resistive device includes a resistor.

38. The method of claim 36 , wherein the short circuit point includes ground.

39. A memory device comprising: a first memory cell including a first access transistor and a first capacitor connected at a first storage node; a second memory cell including a second access transistor and a second capacitor connected at a second storage node; an isolation device including an isolation gate, a first electrode connected to the first storage node, and a second electrode connected to the second storage node; and a current control circuit connected between the isolation gate and a power node for modifying a resistance between the isolation gate and the power node.

40. The memory device of claim 39 , wherein current control circuit is configured to provide a resistance between the isolation gate and the power node for reducing a current flowing between the isolation gate and the power node when a defect occurs to the isolation gate.

41. The memory device of claim 39 , wherein the power node connects to ground.

42. The memory device of claim 39 , wherein the power node connects to a negative voltage.

43. The memory device of claim 39 , wherein each of the first and second access transistors includes a gate dielectric with a gate dielectric thickness, and the isolation device further includes an isolation dielectric with a thickness greater than the gate dielectric thickness.

44. The memory device of claim 39 , wherein each of the first and second access transistors includes an access threshold voltage, and the isolation device further include a threshold voltage greater than the access threshold voltage.

45. The memory device of claim 39 , wherein each of the first and second memory cells has an area of 6F 2 .

46. A memory device comprising: a plurality of memory cells arranged in rows and columns, the rows being arranged in row pairs, each of the row pairs including a first cell row and a second cell row, wherein: each memory cell of the first cell row includes a first access transistor and a first capacitor connected at a first storage node; and each memory cell of the second cell row includes a second access transistor and a second capacitor connected at a second storage node; and a plurality of isolation rows, each of the isolation rows including a plurality of isolation devices, each of the isolation devices including an isolation gate, a first electrode connected to the first storage node, a second electrode connected to the second storage node, each of the isolation devices being configured to provide electrical isolation between the first and second storage nodes; a plurality of isolation lines, each of the isolation lines connecting to the isolation gate of each of the isolation devices of one of the isolation rows, the isolation lines being arranged in M groups, each of the M groups having a group node and having at least one isolation line connected at the group node; and M current control circuits, each of the M current control circuits connecting between a power node and the group node of one of the M groups.

47. The memory device of claim 46 , wherein M equals the number of isolation lines.

48. The memory device of claim 46 , wherein M is at least one.

49. The memory device of claim 46 , wherein each of the M current control circuits is configured to provide a resistance between the power node and a corresponding group node of one of the M groups.

50. The memory device of claim 46 , wherein the current control circuit includes a transistor having a first electrode connected to the isolation line, a second electrode connected to the power node, and a gate connected to bias node.

51. The memory device of claim 46 , wherein power node connects to a positive voltage.

52. The memory device of claim 46 , wherein each of the first and second access transistors includes a gate dielectric with a gate dielectric thickness, and each of the isolation devices further includes an isolation dielectric with a thickness greater than the gate dielectric thickness.

53. The memory device of claim 46 , wherein each of the isolation devices includes an isolation dielectric having a shallow trench isolation structure.

54. The memory device of claim 46 , wherein each of the first and second access transistors includes an access threshold voltage, and each of the isolation devices further includes a threshold voltage greater than the access threshold voltage.

55. The memory device of claim 46 further comprising a plurality of word lines, each of the word lines connecting to a gate of each of the access transistors in one of the rows, and a plurality of bit lines, each of the bit lines connecting to an electrode of each of the access transistors in one of the columns.

56. A memory device comprising: a first memory cell including a first access transistor and a first capacitor, the first access transistor including an electrode connected to the first capacitor via a first storage node formed in a substrate; a second memory cell including a second access transistor and a second capacitor, the second access transistor including an electrode connected to the second capacitor via a second storage node formed on the substrate; an isolation device formed between the first and second storage nodes and configured to providing electrical isolation between first and second storage nodes, the isolation device including an isolation gate; and an isolation line connected to the isolation gate for holding the isolation gate at a positive voltage.

57. The memory device of claim 56 , wherein each of the first and second access transistors includes a gate dielectric with a gate dielectric thickness, and the isolation device further includes an isolation dielectric with an isolation dielectric thickness greater than the gate dielectric thickness.

58. The memory device of claim 56 , wherein each of the first and second access transistors including a gate dielectric formed above the substrate, and the isolation device further includes an isolation dielectric with at least a portion of the isolation dielectric formed within the substrate.

59. The memory device of claim 56 , wherein the isolation dielectric includes an isolation dielectric having a trench formed in the substrate between the first and second storage nodes.

60. The memory device of claim 56 , wherein the first access transistor further includes a second electrode connected to a first bit line contact, and the second access transistor further includes a second electrode connected to a second bit line contact.

61. A memory device comprising: a substrate; a first memory cell including a first access transistor formed by a first doped region and a second doped region of the substrate and by a gate separated from the substrate by a first gate dielectric formed on the substrate opposing a first channel region between the first and second doped regions; a second memory cell including a second access transistor formed by a third doped region and a fourth doped regions of the substrate and by a gate separated from the substrate by a second gate dielectric formed on the substrate opposing a second channel region between the third and fourth doped regions, each of the first and second access transistors having an access threshold voltage; an isolation device formed by the second and third doped regions and by an isolation gate separated from the substrate by an isolation dielectric formed in the substrate between the second and third doped regions, the isolation device having an isolation threshold voltage greater than the access threshold voltage; and an isolation line connected to the isolation gate for holding the isolation gate at a positive voltage.

62. The memory device of claim 61 , wherein: the first memory cell further includes a capacitor having a capacitor plate corresponding to the second doped region; and the second memory cell further includes a capacitor having a capacitor plate corresponding to the third doped region.

63. The memory device of claim 62 , wherein the isolation threshold voltage is at least three times greater than a supply voltage of the memory device.

64. The memory device of claim 61 , wherein a thickness of the isolation dielectric is greater than a thickness of each of the first and second gate dielectrics.

65. The memory device of claim 61 , wherein the isolation dielectric includes a trench formed in the substrate and in between the second and third doped regions.

66. The memory device of claim 61 , wherein the isolation device is configured to be inactive during a normal operation of the memory device.

67. The memory device of claim 61 , wherein a each of the first and fourth doped regions includes a halo implant portion.

68. A system comprising: a processor; and a memory device connected to the processor, the memory device including: a plurality of memory cells arranged in rows and columns, the rows being arranged in row pairs, each of the row pairs including a first cell row and a second cell row, wherein: each memory cell of the first cell row includes a first access transistor and a first capacitor connected at a first storage node; and each memory cell of the second cell row includes a second access transistor and a second capacitor connected at a second storage node; and a plurality of isolation rows, each of the isolation rows including a plurality of isolation devices, each of the isolation devices including an isolation gate, a first electrode connected to the first storage node, a second electrode connected to the second storage node, each of the isolation devices being configured to provide electrical isolation between the first and second storage nodes; a plurality of isolation lines, each of the isolation lines connecting to the isolation gate of each of the isolation devices of one of the isolation rows, the isolation lines being arranged in M groups, each of the M groups having a group node and having at least one isolation line connected at the group node; and M current control circuits, each of the M current control circuits connecting between a power node and the group node of one of the M groups.

69. The system of claim 68 , wherein M equals the number of isolation lines.

70. The system of claim 68 , wherein M is at least one.

71. The system of claim 68 , wherein each of the M current control circuits is configured to provide a resistance between the power node and a corresponding group node of one of the M groups.

72. The system of claim 68 , wherein each of the first and second access transistors includes a gate dielectric with a gate dielectric thickness, and each of the isolation devices includes an isolation dielectric with a thickness greater than the gate dielectric thickness.

73. The system of claim 68 , wherein each of the isolation devices includes an isolation dielectric having a trench formed in the substrate between the first and second storage nodes.

74. The system of claim 68 , wherein each of the first and second access transistors including an access threshold voltage, and each of the isolation devices including a threshold voltage greater than the access threshold voltage.

75. A method comprising: forming a first memory cell including forming a first access transistor and a first capacitor, the first access transistor including an electrode connected to the first capacitor via a first storage node formed on a substrate; forming a second memory cell including forming a second access transistor and a second capacitor, the second access transistor including an electrode connected to the second capacitor via a second storage node formed on the substrate; forming an isolation device between the first and second storage node contacts and configured to provide electrical isolation between first and second storage nodes, wherein forming the isolation device includes forming an isolation gate; and forming a current control circuit between the isolation gate and a power node for modifying the resistance between the isolation gate and the power node.

76. The method of claim 75 , wherein forming each of the first and second memory cells includes forming a gate dielectric with a gate dielectric thickness, and forming the isolation device includes forming an isolation dielectric with an isolation dielectric thickness greater than the gate dielectric thickness.

77. The method of claim 75 , wherein forming an isolation devices includes forming an isolation dielectric having a trench formed in the substrate between the first and second storage nodes.

78. The method of claim 75 , wherein forming each of the first and second memory cells includes forming each of the first and second access transistors with an access threshold voltage, and forming the isolation device includes forming the isolation device with a threshold voltage greater than the access threshold voltage.

79. A method comprising: providing a substrate having a first memory cells area, a second memory cell area, and an isolation device area between the first and second memory cells areas; forming a first memory cell on the first memory cell area, the first memory cell having a first access transistor and a first capacitor connected together at first storage node formed on a substrate; forming a second memory cell on the second memory cell area, the second memory cell having a second access transistor and a second capacitor connected together at a second storage node on the substrate; forming an isolation device on the isolation device area for electrically isolating the first and second memory cells, the isolation device having an isolation gate; and forming an isolation line connecting the isolation gate to a positive voltage.

80. The method of claim 79 , wherein forming the isolation device includes forming an isolation dielectric separating the isolation gate from the substrate, wherein forming the isolation dielectric includes: forming a shallow trench over the isolation device area; and filling the shallow trench with dielectric material.

81. The method of claim 80 , wherein forming each of the first and second memory cells includes forming a gate dielectric above the substrate at each of the first and second transistors.

82. The method of claim 80 further comprising: implanting dopant into the shallow trench before filling the shallow trench.

83. The method of claim 79 , wherein forming each of the first and second memory cells includes: forming the first access transistor having a first electrode connected to the first capacitor via a first diffusion region in the substrate, and having a second electrode connected to a bit line contact via a second diffusion region in the substrate; forming the second access transistor having a first electrode connected to the second capacitor a third diffusion region in the substrate, and a second electrode connected to a second bit line contact a fourth diffusion region in the substrate; and implanting halo implant only in the second and fourth diffusion regions.

84. The method of claim 79 , wherein forming the first and second memory cells include forming each of the first and second access transistors with an access threshold voltage, and forming the isolation device includes forming the isolation device with a threshold voltage greater than the access threshold voltage.