A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor memory device, comprising: memory mats obtained by dividing a memory array into at least two portions; a first peripheral circuit which is provided for each of said respective memory mats, controls said memory mats, and performs a data transfer with said memory mat; a second peripheral circuit for performing overall control of each of said peripheral circuits; a first power control section for controlling a power supply in a non-selected first peripheral circuit when one of said memory mats divided into at least two portions is selected and operated; and a second power control section for controlling a power supply in said first power control section and said second peripheral circuit when either of said memory mat divided into at least two portions is not selected.
2. The semiconductor memory device according to claim 1 , wherein said second power control section comprises: a second switch control circuit for outputting a control signal when a standby signal is inputted; and a second switch section for shutting off the power supply to said second peripheral circuit based on the control signal of said second switch control circuit.
3. The semiconductor memory device according to claim 1 , wherein said first power control section comprises: a first switch control circuit for outputting a control signal based on a memory mat selection signal outputted from a predecoder circuit provided in said second peripheral circuit; and a first switch section for shutting off the power supply to said first peripheral circuit based on the control signal of said first switch control circuit.
4. The semiconductor memory device according to claim 3 , wherein, among the peripheral circuits provided in said first peripheral circuit, the first switch section connected to said peripheral circuit which outputs a Hi signal at an active time is connected between said peripheral circuit and a reference potential, and said peripheral circuit outputs a Lo signal when a power supply is shut off by said first switch section.
5. The semiconductor memory device according to claim 1 , comprising: a switch control section for turning off said first switch section based on the control signal outputted from said first and second switch control circuits when the standby signal is inputted, wherein said first switch section shuts off the power supply to said first peripheral circuit at the standby time by the control of said switch control section.
6. A semiconductor integrated circuit device, comprising a memory module which includes: memory mats obtained by dividing a memory array into at least two portions; a first peripheral circuit which is provided for each of said respective memory mats, controls said memory mats, and performs a data transfer with said memory mat; a second peripheral circuit for performing overall control of each of said peripheral circuits; a first power control section for controlling a power supply in a non-selected first peripheral circuit when one of the memory mats divided into at least two portions is selected and operated; and a second power control section for controlling a power supply in said first power control section and said second peripheral circuit when either of said memory mats divided into at least two portions is not selected.
7. The semiconductor integrated circuit device according to claim 6 , wherein said second power control section comprises: a second switch control circuit for outputting the control signal when the standby signal is inputted; and a second switch section for shutting off the power supply to said second peripheral circuit based on the control signal of said second switch control circuit.
8. The semiconductor integrated circuit device according to claim 6 , wherein said first power control section comprises: a first switch control circuit for outputting a control signal based on a memory mat selection signal outputted from a predecoder circuit provided in said second peripheral circuit; and a first switch section for shutting off the power supply to said first peripheral circuit based on the control signal of said first switch control circuit.
9. The semiconductor integrated circuit device according to claim 8 , wherein, among the peripheral circuits provided in said first peripheral circuit, the first switch section connected to said peripheral circuit which outputs a Hi signal at an active time is connected between said peripheral circuit and a reference potential and said peripheral circuit outputs a Lo signal when a power supply is shut off by said first switch section.
10. The semiconductor integrated circuit device according to claim 6 , comprising: a switch control section for turning off said first switch section based on the control signal outputted from said first and second switch control circuit when the standby signal is inputted, wherein said first switch section shuts off the power supply to said first peripheral circuit at the standby time by the control of said switch control section.
11. A semiconductor integrated circuit device composed of a plurality of circuit modules, comprising: a first circuit block having a first circuit module; a second circuit block having a second circuit module; a third circuit block having a third circuit module; a first power control section for controlling a power supply in said first circuit block by a first control signal from a central processing unit in said second circuit block; and a second power control section for controlling a power supply in said first power control section and said second circuit block by a second control signal from said central processing unit.
12. The semiconductor integrated circuit device according to claim 11 , wherein the second power control section controls the power supply by the second control signal representing a standby state of the central processing unit.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 27, 2004
April 18, 2006
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