A parallel processor capable of establishing synchronization among programs executed in parallel, wherein a processor element suspends its processing and enters a waiting state when a wait instruction “sleep” is executed in a user program Prg_d and resumes the processing by releasing the above waiting state based on execution of a wait release instruction “cont(Prg_d)” by another processor element and wherein the latter processor element executes a next instruction without suspending its processing after executing the wait release instruction “cont(Prg_d)”.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A parallel processor comprising: a plurality of processor elements; a first processor element of said plurality of processor elements for executing a first user program of a plurality of user programs, said first processor element executing a wait instruction, said wait instruction suspending processing of said first user program; a second processor element of said plurality of processor elements for executing at least a second user program of said plurality of user programs, said second processor element executing a wait release instruction, said wait release instruction commanding said first processor element to resume said processing of said first user program, said second processor element continuing processing of said second user program after executing said wait release instruction; a plurality of local memory, each local memory being uniquely associated with a corresponding processor element of said plurality of processor elements; and a common memory connected to a common bus, said common memory storing said plurality of user programs, a corresponding user program of said plurality of user programs being provided to said corresponding processor element via said common bus, wherein: said second processor element executes a synchronization wait instruction, said synchronization wait instruction suspending processing of said second user program; said first processor element executes a program end instruction, said program end instruction resuming said processing of said second user program; said wait instruction resumes processing of said second user program after said second processor element executes said synchronization wait instruction; said first processor element notifies said second processor element that said first processor element is executing said wait instruction; and said second processor element executes a program execution instruction, said program execution instruction commanding said corresponding processor element to receive said corresponding user program from said common memory and to execute said corresponding user program.
2. A parallel processor as set forth in claim 1 , wherein said plurality of processor elements and a common bus for connecting said plurality of processor elements are installed in a single semiconductor chip.
3. A parallel processor as set forth in claim 1 , wherein said plurality of processor elements perform mutually parallel processing on the basis of instructions written in a program; and said plurality of processor elements are capable of communicating with each other via a common bus.
4. A parallel processor as set forth in claim 1 , further comprising another processor element of said plurality of processor elements for executing another user program, said another processor element executing a program end instruction, said program end instruction resuming said processing of said second user program.
5. A parallel processor as set forth in claim 1 , wherein said first processor element is said corresponding processor element and said first user program is said corresponding user program.
6. A parallel processor as set forth in claim 1 , wherein said local memory continues to store said user program until said corresponding processor element executes a program end instruction indicating an end of a program.
7. A parallel processor as set forth in claim 1 , wherein, when said second processor element enters a waiting state based on said wait instruction, said corresponding processor element which executed said program execution instruction executes said wait release instruction.
8. A parallel processor as set forth in claim 1 , further comprising: an arbiter for determining which of said plurality of processor elements executes a program instructed to be executed by said program execution instruction, and for reading the program instructed to be executed by said program execution instruction from said common memory to said local memory associated with said corresponding processor element.
9. A parallel processing method comprising: suspending processing of a first user program of a plurality of user programs, said first user program including a wait instruction, a first processor element executing said wait instruction to suspend said processing of said first user program; resuming said processing of said first user program by executing a wait release instruction, said wait release instruction being included within a second user program of a plurality of user programs, a second processor element of said plurality of processor elements for executing said wait release instruction, said wait release instruction commanding said first processor element to resume said processing of said first user program, said second processor element continuing processing of said second user program after executing said wait release instruction; suspending processing of said second user program, said second processor element executing a synchronization wait instruction; and executing a program end instruction to resume said processing of said second user program, said first processor element executing said program end instruction, wherein: said wait instruction resumes processing of said second user program after said second processor element executes said synchronization wait instruction; said first processor element notifies said second processor element that said first processor element is executing said wait instruction; a plurality of local memory, each local memory is uniquely associated with a corresponding processor element of said plurality of processor elements; a common memory connected to a common bus, said common memory storing said plurality of user programs, a corresponding user program of said plurality of user programs being provided to said corresponding processor element via said common bus; and said second processor element executes a program execution instruction, said program execution instruction commanding said corresponding processor element to receive said corresponding user program from said common memory and to execute said corresponding user program.
10. A parallel processing method as set forth in claim 9 , wherein, when said second processor element enters a waiting state based on said wait instruction, said corresponding processor element which executed said program execution instruction executes said wait release instruction.
11. A parallel processing method as set forth in claim 9 , wherein: said second processor element executes a program execution instruction, said program execution instruction commanding said corresponding processor element to receive said corresponding user program from said common memory and to execute said corresponding user program.
12. A storage medium for storing, in a computer-readable format the method of claim 9 .
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 19, 1999
April 18, 2006
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