A method of fabricating a semiconductor device includes forming an interlayer insulating film on a semiconductor element; forming a polysilicon layer on the interlayer insulating film; implanting dopant atoms into the polysilicon layer; forming a resist layer on the polysilicon layer; forming one or more first openings in the resist layer; etching the polysilicon layer using the resist layer as a first mask, thereby forming one or more second openings in the polysilicon layer; and forming one or more contact holes in the interlayer insulating film using at least the polysilicon layer as a second mask.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of fabricating a semiconductor device comprising: forming a first layer on a semiconductor element; forming a second layer on said first layer, said second layer being made of a material having an etching rate which changes in accordance with kind and concentration of dopant atoms implanted therein; implanting dopant atoms into said second layer; forming a third layer on said second layer; forming one or more first openings in said third layer; etching said second layer using said third layer as a first mask, thereby forming one or more second openings in said second layer; and forming one or more contact holes in said first layer using at least said second layer as a second mask, wherein a plurality of said first openings are formed in said third aver as having a same diameter, during said forming one or more first openings, a plurality of said second openings are formed in said second layer as having different diameters, during said etching, and a plurality of said contact holes are formed in said first layer including at least one large-diameter contact hole and at least one small-diameter contact hole, during said forming one or more contact holes.
2. The method according to claim 1 , wherein said first mask used during said forming one or more contact holes has a multilayer structure including said second layer and said third layer.
3. The method according to claim 1 , further comprising: annealing said second layer after said implanting dopant atoms, thereby activating said dopant atoms.
4. The method according to claim 1 , wherein said implanting dopant atoms is performed so that said dopant atoms are implanted into a whole area of said second layer.
5. The method according to claim 1 , wherein said first layer is an interlayer insulating film.
6. The method according to claim 1 , wherein said second layer is a polysilicon layer.
7. The method according to claim 1 , wherein said second layer is a dielectric material.
8. The method according to claim 1 , wherein said third layer is a resist layer.
9. The method according to claim 1 , wherein said forming one or more first openings in said third layer is performed using photolithography.
10. The method according to claim 1 , wherein said dopant atoms are either group V atoms or group III atoms.
11. The method according to claim 1 , wherein said semiconductor element has a gate, a source and a drain; said at least one large-diameter contact hole is formed directly above said gate; and said at least one small-diameter contact hole is formed directly above at least one of said source and said drain.
12. A method of fabricating a semiconductor device comprising: forming a first layer on a semiconductor element; forming a second layer on said first layer, said second layer being made of a material having an etching rate which changes in accordance with kind and concentration of dopant atoms implanted therein; implanting dopant atoms into said second layer; forming a third layer on said second layer; forming one or more first openings in said third layer; etching said second layer using said third layer as a first mask, thereby forming one or more second openings in said second layer; and forming one or more contact holes in said first layer using at least said second layer as a second mask, wherein said implanting dopant atoms is performed so that said dopant atoms are implanted into said second layer inside a specific area and are not implanted into said second layer outside said specific area, and said forming one or more first openings is performed so that at least one of said first openings is formed in said third layer inside said specific area and others of said first openings are formed in said third layer outside said specific area.
13. A method of fabricating a semiconductor device comprising: forming a first layer on a semiconductor element; forming a second layer on said first layer, said second layer being made of a material having an etching rate which changes in accordance with kind and concentration of dopant atoms implanted therein; implanting dopant atoms into said second layer; forming a third layer on said second layer; forming one or more first openings in said third layer; etching said second layer using said third layer as a first mask, thereby forming one or more second openings in said second layer; and forming one or more contact holes in said first layer using at least said second layer as a second mask, wherein said implanting dopant atoms is performed so that said dopant atoms include first dopant atoms and second dopant atoms different from said first dopant atoms, said first dopant atoms are implanted into said second layer inside a specific area, and said second dopant atoms are implanted into said second layer outside said specific area, and said forming one or more first openings is performed so that at least one of said first openings is formed in said third layer inside said specific area and others of said first openings are formed in said third layer outside said specific area.
14. The method according to claim 13 , wherein said first dopant atoms are group V atoms and said second dopant atoms are group III atoms.
15. The method according to claim 13 , wherein said first mask used during said forming one or more contact holes has a multilayer structure including said second layer and said third layer.
16. The method according to claim 13 , further comprising: annealing said second layer after said implanting dopant atoms, thereby activating said dopant atoms.
17. The method according to claim 13 , wherein said first layer is an interlayer insulating film.
18. The method according to claim 13 , wherein said second layer is a polysilicon layer.
19. The method according to claim 13 , wherein said second layer is a dielectric material.
20. The method according to claim 13 , wherein said third layer is a resist layer.
21. The method according to claim 13 , wherein said forming one or more first openings in said third layer is performed using photolithography.
22. The method according to claim 13 , wherein said dopant atoms are either group V atoms or group III atoms.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 16, 2003
May 9, 2006
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