Apparatus and method for step-down switching voltage regulation

1. A circuit for switched buck regulation, comprising: an inductor circuit that is arranged to provide an inductor current; a capacitor circuit that is arranged to provide an output voltage from the inductor current; a bottom-side switch circuit that is coupled between a ground node and the inductor circuit, wherein the bottom-side switch is arranged to open and close responsive to a first switch control signal; a top-side switch circuit that is coupled between the inductor circuit and an input node, wherein the top-side switch circuit is configured to receive an input voltage at the input node, and wherein the top-side switch circuit is arranged to open and close responsive to a second switch control signal; a current sense amplifier circuit that is arranged to sense a current across the bottom-side switch circuit, and further arranged to provide a current sense voltage in response to the current, wherein the current sense voltage is approximately proportional to the sensed current; a sample-and-hold circuit that is arranged to sample the current sense voltage if the bottom-side switch is closed, and further arranged to hold the current sense voltage if the bottom-side switch is open, wherein the sample-and-hold circuit is arranged to provide a sample-and-hold signal; and a switch control circuit that is configured to provide the first and second switch control signals based in part on the sample-and-hold signal and the output voltage.

2. The circuit of claim 1 , wherein the top-side switch circuit includes a transistor, and wherein the bottom-side switch circuit includes another transistor.

3. The circuit of claim 1 , wherein the sample-and-hold circuit includes a switched capacitor.

4. A circuit for switched buck regulation comprising: an inductor circuit that is arranged to provide an inductor current; a capacitor circuit that is arranged to provide an output voltage from the inductor current; a bottom-side switch circuit that is coupled between a ground node and the inductor circuit, wherein the bottom-side switch is arranged to open and close responsive to a first switch control signal; a top-side switch circuit that is coupled between the inductor circuit and an input node, wherein the top-side switch circuit is configured to receive an input voltage at the input node, and wherein the top-side switch circuit is arranged to open and close responsive to a second switch control signal; a current sense amplifier circuit that is arranged to sense a current across the bottom-side switch circuit, and further arranged to provide a current sense voltage in response to the current; a sample-and-hold circuit that is arranged to sample the current sense voltage if the bottom-side switch is closed, and further arranged to hold the current sense voltage if the bottom-side switch is open, wherein the sample-and-hold circuit is arranged to provide a sample-and-hold signal; a switch control circuit that is configured to provide the first and second switch control signals based in part on the sample-and-hold signal and the output voltage; and a resistor that is arranged such that a voltage across the resistor is substantially equal to the difference between the input voltage and the output voltage, and further arranged to provide a resistor current from the voltage across the resistor.

5. A circuit for switched buck regulation, comprising: an inductor circuit that is arranged to provide an inductor current; a capacitor circuit that is arranged to provide an output voltage from the inductor current; a bottom-side switch circuit that is coupled between a ground node and the inductor circuit, wherein the bottom-side switch is arranged to open and close responsive to a first switch control signal; a top-side switch circuit that is coupled between the inductor circuit and an input node, wherein the top-side switch circuit is configured to receive an input voltage at the input node, and wherein the top-side switch circuit is arranged to open and close responsive to a second switch control signal; a current sense amplifier circuit that is arranged to sense a current across the bottom-side switch circuit, and further arranged to provide a current sense voltage in response to the current; a sample-and-hold circuit that is arranged to sample the current sense voltage if the bottom-side switch is closed, and further arranged to hold the current sense voltage if the bottom-side switch is open, wherein the sample-and-hold circuit is arranged to provide a sample-and-hold signal; a switch control circuit that is configured to provide the first and second switch control signals based in part on the sample-and-hold signal and the output voltage; a resistor that is arranged such that a voltage across the resistor is substantially equal to the difference between the input voltage and the output voltage, and further arranged to provide a resistor current from the voltage across the resistor; and a current source circuit that is arranged to mirror the resistor current to provide a charge current to a ramp generator.

6. The circuit of claim 5 , wherein the current source circuit includes: a first current source that is arranged to mirror the resistor current to provide another current; and a second current source that is arranged to mirror the other current to provide the charge current to the ramp generator.

7. The circuit of claim 6 , further comprising: an operational amplifier circuit that is coupled to the resistor at a first node, wherein the resistor is coupled between the input node and the first node, and wherein the operational amplifier circuit is arranged to adjust a base voltage that is associated with the first current source such that a voltage that is associated with the first node is approximately equal to the output voltage.

8. The circuit of claim 5 , wherein the ramp generator current is arranged to provide a voltage ramp signal based on the ramp generator current and a sensed signal that is based on the sample-and-hold signal.

9. The circuit of claim 8 , wherein the ramp generator circuit is further arranged to be responsive to a reset signal such that the ramp signal substantially discharges to a voltage that is associated with the sensed signal when the reset signal is asserted, and such that the ramp signal substantially linearly increases when the reset signal is unasserted such that the linear increase is substantially similar to a linear increase that is associated with the inductor current.

10. The circuit of claim 8 , wherein the ramp generator circuit includes: a ramp generator capacitor circuit that is coupled between second and third nodes, wherein the capacitor circuit is arranged to receive the ramp generator current at the second node, and further arranged to receive the sensed signal at the third node; and a switch circuit that is arranged to discharge the ramp generator capacitor circuit if a reset signal is asserted.

11. A circuit for switched buck regulation, comprising: an inductor circuit that is arranged to provide an inductor current; a capacitor circuit that is arranged to provide an output voltage from the inductor current; a bottom-side switch circuit that is coupled between a ground node and the inductor circuit, wherein the bottom-side switch is arranged to open and close responsive to a first switch control signal; a top-side switch circuit that is coupled between the inductor circuit and an input node, wherein the top-side switch circuit is configured to receive an input voltage at the input node, and wherein the top-side switch circuit is arranged to open and close responsive to a second switch control signal; a current sense amplifier circuit that is arranged to sense a current across the bottom-side switch circuit, and further arranged to provide a current sense voltage in response to the current; a sample-and-hold circuit that is arranged to sample the current sense voltage if the bottom-side switch is closed, and further arranged to hold the current sense voltage if the bottom-side switch is open, wherein the sample-and-hold circuit is arranged to provide a sample-and-hold signal; a switch control circuit that is configured to provide the first and second switch control signals based in part on the sample-and-hold signal and the output voltage; a resistor; a current source circuit; and a ramp generator circuit that is configured to provide a voltage ramp signal, wherein the resistor, current source circuit, and ramp generator circuit are arranged such that the voltage ramp signal has an upslope that is substantially similar to an upslope that is associated with another upslope that is associated with the inductor current.

12. The circuit of claim 11 , wherein a voltage across the resistor is substantially equal to difference between the input voltage and the output voltage.

13. The circuit of claim 11 , wherein the ramp generator signal includes a capacitor, and wherein the capacitor is arranged to discharge if a reset signal is asserted.

14. The circuit of claim 11 , wherein the switch control circuit includes a pulse width modulation comparator that is configured to provide the second control signal based on a comparison between the voltage ramp signal and a comparison signal, wherein the comparison signal is based in part on the output voltage.

15. The circuit of claim 14 , wherein the switch control circuit further includes a voltage divider circuit that is arranged to provide a sensed voltage from the output voltage.

16. The circuit of claim 15 , wherein the switch control circuit further includes an error amplifier circuit that is arranged to provide the comparison signal from the sensed voltage and a reference voltage.

17. A circuit for switched buck regulation, comprising: an inductor circuit that is coupled between a switch node and an output node; a capacitor circuit that is coupled to the output node; a bottom-side switch circuit that is coupled between a ground node and the switch node; a top-side switch circuit that is coupled between switch node and an input node; a current sense amplifier circuit including a first input that is coupled to the switch node, and further including a second input that is coupled to the ground node; a sample-and-hold circuit including an input that is coupled to an output of the current sense amplifier circuit; and a switch control circuit including a first input that is coupled to an output of the sample-and-hold circuit, another input that is coupled to the output node, a first output that is coupled to the top-side switch circuit, and a second output that is coupled to the bottom-side switch circuit.

18. A circuit for switched buck regulation, comprising: an inductor circuit that is coupled between a switch node and an output node; a capacitor circuit that is coupled to the output node; a bottom-side switch circuit that is coupled between a ground node and the switch node; a top-side switch circuit that is coupled between switch node and an input node; a current sense amplifier circuit including a first input that is coupled to the switch node, and further including a second input that is coupled to the ground node; a sample-and-hold circuit including an input that is coupled to an output of the current sense amplifier circuit; a switch control circuit including a first input that is coupled to an output of the sample-and-hold circuit, another input that is coupled to the output node, a first output that is coupled to the top-side switch circuit, and a second output that is coupled to the bottom-side switch circuit; a current source circuit that includes a first current source; a resistor that is coupled between the input node and a collector that is associated with the first current source; and a ramp generator circuit that is coupled to the current source circuit, the sample-and-hold circuit, and the switch control circuit.

19. The circuit of claim 18 , wherein the switch control circuit includes: a resistor divider circuit that is coupled to the output node; an error amplifier circuit that is coupled to the resistor divider circuit; and a PWM comparator circuit including a first input that is coupled to the error amplifier and a second input that is coupled to the ramp generator circuit.

20. A circuit for switched buck regulation, comprising: a means for providing a ramping current; a means for providing an output voltage from the ramping current; a means for coupling a ground node to the means for providing the ramping current if a first switch control signal is asserted; a means for coupling an input node to the means for providing the ramping current if a second switch control signal is asserted; a means for sensing a current across the means for coupling the ground node to the means for providing the ramping current; a means for providing a current sense voltage in response to the current, wherein the current sense voltage is approximately proportional to the current; a means for sampling the current sense voltage if the means for providing the ramping current is coupled to the ground node; a means for holding the current sense voltage if the means for providing the ramping current is coupled to the input node; and a means for providing the first and second switch control signals based in part on the current sense voltage and the output voltage.

21. A circuit for voltage regulation, comprising: a switch control circuit that is operable to provide a first switch control signal to a first switch, and to provide a second switch control signal to a synchronous switch, such that the first and second control signals are based in part on a sample-and-hold signal and an output voltage; a current sense circuit that is operable to sense a current across the synchronous switch, and to provide a current sense voltage at a current sense node in response to the sensed current; and a sample-and-hold circuit that is operable to sample the current sense voltage if the synchronous switch is closed, and further arranged to hold the current sense voltage if the synchronous switch is open, wherein the sample-and-hold circuit is arranged to provide the sample-and-hold signal at a capacitor node, and wherein the sample-and-hold circuit includes: a switch that is coupled between the current sense node and a capacitor node, wherein the switch is operable to close if the synchronous switch is closed, and to open if the synchronous switch is open.