A MOSFET device and method of fabricating are disclosed. The present invention utilizes Schottky barrier contacts for source and/or drain contact fabrication within the context of a MOSFET device structure to eliminate the requirement for halo/pocket implants and shallow source/drain extensions to control short channel effects. Additionally, the present invention unconditionally eliminates the parasitic bipolar gain associated with MOSFET fabrication, reduces manufacturing costs, tightens control of device performance parameters, and provides for superior device characteristics as compared to the prior art.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of fabricating a short-channel length CMOS device on a semiconductor substrate, the method comprising: introducing N-type dopants into a first channel region such that a first dopant concentration profile varies in the vertical direction and is generally constant in the lateral direction; introducing P-type dopants into a second channel region of the semiconductor substrate, such that a second dopant concentration profile varies in the vertical direction and is generally constant in the lateral direction; forming a first source electrode and a first drain electrode both having a first Schottky barrier contact adjacent the first channel region such that a first channel length is less than about 100 nm; and forming a second source electrode and a second drain electrode both having a second Schottky barrier contact adjacent the second channel region, such that the second channel length is less than about 100 nm.
2. The method of claim 1 further comprising providing a first gate electrode over the first channel region, and providing a second gate electrode over the second channel region.
3. The method of claim 2 wherein the first source and drain electrodes are formed by the steps comprising: exposing the semiconductor substrate on one or more areas proximal to the first gate electrode; depositing a first thin film of metal; reacting the first metal with the exposed semiconductor substrate such that a first source electrode and drain electrode are formed having the first Schottky barrier contact adjacent the first channel region; and removing the unreacted first metal.
4. The method of claim 2 wherein the second source and drain electrodes are formed by the steps comprising: exposing the semiconductor substrate on one or more areas proximal to the second gate electrode; depositing a second thin film of metal; reacting the second metal with the exposed semiconductor substrate such that a second source electrode and drain electrode are formed having the second Schottky barrier contact adjacent the second channel region; and removing the unreacted second metal.
5. The method of claim 2 wherein the first gate electrode is provided by the steps comprising: providing a thin insulating layer on the semiconductor substrate; depositing a first thin conducting film on the insulating layer; patterning and etching the first conducting film to form the first gate electrode; and forming one or more thin insulating layers on one or more sidewalls of the first gate electrode.
6. The method of claim 2 wherein the second gate electrode is provided by the steps comprising: providing a thin insulating layer on the semiconductor substrate; depositing a second thin conducting film on the insulating layer; patterning and etching the second conducting film to form the second gate electrode; and forming one or more thin insulating layers on one or more sidewalls of the second gate electrode.
7. The method of claim 3 wherein the reacting step is performed by thermal annealing.
8. The method of claim 1 wherein the first source electrode and the drain electrode are formed from a member of the group consisting of: Platinum Silicide, Palladium Silicide and Iridium Silicide; and further wherein the N-type channel dopants are selected from the group consisting of: Arsenic, Phosphorous, and Antimony.
9. The method of claim 1 wherein the second source electrode and the drain electrode are formed from a member of the group consisting of the rare-earth suicides, and further wherein the P-type channel dopants are selected from the group consisting of: Boron, Indium, and Gallium.
10. The method of claim 5 wherein the first thin conducting film of the first gate electrode is formed of Boron doped polysilicon.
11. The method of claim 6 wherein the second thin conducting film of the second gate electrode is formed of Phosphorous doped polysilicon.
12. The method of claim 2 wherein an entire surface of the at least one of the first source electrode and drain electrode forms a Schottky or Schottky-like contact with the semiconductor substrate.
13. The method of claim 2 wherein an entire surface of the at least one of the second source electrode and drain electrode forms a Schottky or Schottky-like contact with the semiconductor substrate.
14. The method of claim 2 wherein the first gate electrode is provided after the completion of all channel doping processes.
15. The method of claim 2 wherein the second gate electrode is provided after the completion of all channel doping processes.
16. A method of fabricating a short-channel length CMOS device on a semiconductor substrate, the method comprising: introducing N-type dopants into a first channel region and P-type dopants into a second channel region of the semiconductor substrate, such that the dopant concentration varies in the vertical direction and is generally constant in the lateral direction; and forming a first source electrode and a first drain electrode both having a first Schottky baffler contact adjacent the first channel region and a second source electrode and a second drain electrode both having a second Schottky baffler contact adjacent the second channel region, such that both a first channel length and a second channel length are less than about 100 nm.
17. The method of claim 16 further comprising providing a first gate electrode over the first channel region, and providing a second gate electrode over the second channel region.
18. The method of claim 16 wherein the first source electrode and the drain electrode are formed from a member of the group consisting of: Platinum Silicide, Palladium Silicide and Iridium Silicide.
19. The method of claim 18 wherein the N-type channel dopants are selected from the group consisting of: Arsenic, Phosphorous, and Antimony.
20. The method of claim 16 wherein the second source electrode and the drain electrode are formed from a member of the group consisting of the rare-earth silicides; and further wherein the P-type channel dopants are selected from the group consisting of: Boron, Indium, and Gallium.
21. A method of fabricating a short-channel length CMOS device on a semiconductor substrate, the method comprising: introducing N-type dopants into a first channel region such that a first dopant concentration profile varies in the vertical direction and is generally constant in the lateral direction; introducing P-type dopants into a second channel region of the semiconductor substrate, such that a second dopant concentration profile varies in the vertical direction and is generally constant in the lateral direction; providing a first gate electrode over the first channel region; providing a second gate electrode over the second channel region; forming a first source electrode and a first drain electrode both having a first Schottky barrier contact at least adjacent to the first channel region such that a first channel length is less than about 100 nm; and forming a second source electrode and a second drain electrode both having a second Schottky barrier contact at least adjacent to the second channel region, such that the second channel length is less than about 100 nm.
22. The method of claim 21 wherein the first and second source and drain electrodes are provided by the steps comprising: exposing the semiconductor substrate on one or more areas proximal to the first gate electrode; depositing a first thin film of metal; reacting the first metal with the exposed semiconductor substrate such that a first source electrode and drain electrode are formed having the first Schottky baffler contact adjacent the first channel region; removing the unreacted first metal; exposing the semiconductor substrate on one or more areas proximal to the second gate electrode; depositing a second thin film of metal; reacting the second metal with the exposed semiconductor substrate such that a second source electrode and drain electrode are formed having the second Schottky baffler contact adjacent the second channel region; and removing the unreacted second metal.
23. The method of claim 21 wherein the first and second gate electrodes are provided by the steps comprising: providing a thin insulating layer on the semiconductor substrate; providing a first thin conducting film on the insulating layer in at least a portion of regions having N-type doping in the semiconductor substrate; patterning and etching the first conducting film to form the first gate electrode. providing a second thin conducting film on the insulating layer in at least a portion of regions having P-type doping in the semiconductor substrate; and patterning and etching the second conducting film to form the second gate electrode.
24. The method of claim 23 wherein a sidewall is provided on the first and second gate electrodes by the step comprising: forming one or more thin insulating layers on one or more sidewalls of the first gate electrode and the second gate electrode.
25. The method of claim 22 wherein the reacting step is performed by thermal annealing.
26. The method of claim 21 wherein the first source electrode and the drain electrode are formed from a member of the group consisting of: Platinum Silicide, Palladium Silicide and Iridium Silicide; and further wherein the N-type channel dopants are selected from the group consisting of: Arsenic, Phosphorous, and Antimony.
27. The method of claim 21 wherein the second source electrode and the drain electrode are formed from a member of the group consisting of the rare-earth silicides, and further wherein the P-type channel dopants are selected from the group consisting of: Boron, Indium, and Gallium.
28. The method of claim 23 wherein the first thin conducting film is formed of Boron doped polysilicon and the second conducting film is formed of Phosphorous doped polysilicon.
29. The method of claim 21 wherein an entire surface of the at least one of the first source electrode and drain electrode forms a first Schottky or Schottky-like contact with the semiconductor substrate.
30. The method of claim 21 wherein an entire surface of the at least one of the second source electrode and drain electrode forms a second Schottky or Schottky-like contact with the semiconductor substrate.
31. The method of claim 21 wherein the first Schottky or Schottky-like contact of the at least one of the first source electrode and drain electrodes is formed at least in areas adjacent to the first channel.
32. The method of claim 21 wherein the second Schottky or Schottky-like contact of the at least one of the second source electrode and drain electrodes is formed at least in areas adjacent to the second channel.
33. The method of claim 21 wherein the first gate electrode is provided after the completion of all channel doping processes.
34. The method of claim 21 wherein the second gate electrode is provided after the completion of all channel doping processes.
35. The method of claim 21 wherein the first gate electrode has a length not exceeding 100 nm.
36. The method of claim 21 wherein the second gate electrode has a length not exceeding 100 nm.
37. The method of claim 21 wherein the first and second source and drain electrodes are provided by the steps comprising: exposing the semiconductor substrate on one or more areas proximal to the first gate electrode and one or more areas proximal to the second gate electrode; providing an interfacial layer at least in the exposed semiconductor substrate regions; exposing the semiconductor substrate at least on one ore more areas proximal to the first gate electrode; depositing a first thin film of metal; reacting the first metal with the exposed semiconductor substrate such that a first metal source electrode and drain electrode are formed having a first Schottky-like contact adjacent the first channel region, the first Schottky-like contact having an interfacial layer between the first metal source and/or drain and the channel region; removing the unreacted first metal; exposing the semiconductor substrate at least on one or more areas proximal to the second gate electrode; depositing a second thin film of metal; reacting the second metal with the exposed semiconductor substrate such that a second metal source electrode and drain electrode are formed having a second Schottky-like contact adjacent the second channel region, the second Schottky-like contact having an interfacial layer between the second metal source and/or drain and the channel region; and removing the unreacted second metal.
38. The method of claim 37 wherein the interfacial layer is an insulator.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 7, 2003
May 30, 2006
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