Nonvolatile semiconductor memory

1. A nonvolatile semiconductor memory having a plurality of common control gate lines, a plurality of bit lines and a source line comprising: a memory cell array including a memory cell block comprising a plurality of memory cell units arranged in parallel with each other in a row direction, each of the memory cell unit comprising: a plurality of memory cell transistors arranged in a column line; a first select gate transistor connected to the bit line at a first end of each of the memory cell transistors; and a second select gate transistor connected to the source line at a second end of each of the memory cell transistors so that the memory cell transistors arranged in a row can be connected to the common control gate line; and a control gate line drive circuit configured to simultaneously write-in all of the memory cell transistors connected to a selected control gate line, wherein different types of voltages incapable of write-in applied at least once to all or a part of the control gate lines before applying a high plus voltage for write-in to the selected control gate line.

2. The nonvolatile semiconductor memory of claim 1 , wherein a predetermined low channel voltage is applied for a selected memory cell transistor in a selected memory cell unit to perform write-in by the control gate line drive circuit, when a high plus voltage is applied to the selected control gate line; and a voltage self-boosted from the channel voltage is applied for an unselected memory transistor to restrict write-in by the control gate line drive circuit, the unselected memory transistor is connected to the selected control gate line, through capacitive coupling to one to a plurality of control gate lines.

3. The nonvolatile semiconductor memory of claim 2 , wherein a reference voltage is applied to the control gate line to which the different types of voltages have been applied, once the different types of voltages incapable for write-in are applied.

4. The nonvolatile semiconductor memory of claim 3 , wherein, when sequentially writing to all control gate lines in the selected memory cell block, write-in is performed by selecting in order from a first control gate line from the source line side towards the bit line side.

5. The nonvolatile semiconductor memory of claim 4 , wherein the voltage incapable for write-in is a single type of voltage.

6. The nonvolatile semiconductor memory of claim 5 , wherein a time necessary for applying the voltage incapable for write-in varies depending on the control gate line.

7. The nonvolatile semiconductor memory of claim 6 , wherein the time necessary for applying the voltage incapable for write-in to an unselected control gate line is shorter than time necessary for applying the voltage incapable for write-in to the selected control gate line.

8. The nonvolatile semiconductor memory of claim 6 , wherein the time necessary for applying the voltage incapable for write-in to an unselected control gate line that is arranged on the bit line side is shorter than time necessary for applying the voltage incapable for write-in to the selected control gate line and an unselected control gate line that is arranged further along the source line side than the selected control gate line.

9. A nonvolatile semiconductor memory having a plurality of common control gate lines, a plurality of bit lines and a source line comprising: a memory cell array including a memory cell block comprising a plurality of memory cell units arranged in parallel with each other in a row direction, each of the memory cell unit comprising: a plurality of memory cell transistors arranged in a column line; a first select gate transistor connected to the bit line at a first end of each of the memory cell transistors; and a second select gate transistor connected to the source line at a second end of each of the memory cell transistors so that the memory cell transistors arranged in a row can be connected to the common control gate line; and a control gate line drive circuit configured to simultaneously write-in all of the memory cell transistors connected to a selected control gate line, wherein, before applying a plus first voltage intended for write-in to the selected control gate line, and applying a second voltage intended for boosting a channel voltage to at least a part or all of unselected control gate lines, a third voltage incapable for write-in is applied at least once to all or a part of the control gate lines.

10. The nonvolatile semiconductor memory of claim 9 , wherein, a predetermined low channel voltage is applied for a selected memory cell transistor in a selected memory cell unit to perform write-in by the control gate line drive circuit, when a high plus voltage is applied to the selected control gate line; and a voltage self-boosted from the channel voltage is applied for an unselected memory transistor to restrict write-in by the control gate line drive circuit, the unselected memory transistor is connected to the selected control gate line, through capacitive coupling to one to a plurality of control gate lines.

11. The nonvolatile semiconductor memory of claim 10 , wherein, a reference voltage is applied to the control gate line to which the third voltage has been applied, once the third voltage is applied.

12. The nonvolatile semiconductor memory of claim 11 , wherein, when sequentially writing to all control gate lines in the selected memory cell block, write-in is performed while selecting in order from a first control gate line from the source line side towards the bit line side.

13. The nonvolatile semiconductor memory of claim 12 , wherein a time necessary for applying the third voltage varies depending on the control gate line.

14. The nonvolatile semiconductor memory of claim 13 , wherein the time necessary for applying the third voltage to an unselected control gate line is shorter than time necessary for applying the third voltage to the selected control gate line.

15. The nonvolatile semiconductor memory of claim 13 , wherein the time necessary for applying the third voltage to an unselected control gate line, which is arranged on the bit line side, is shorter than time necessary for applying the third voltage to the selected control gate line and an unselected control gate line, which is arranged further on the source line side than the selected control gate line.

16. A nonvolatile semiconductor memory having a plurality of common control gate lines, a plurality of bit lines and a source line comprising: a memory cell array including a memory cell block comprising a plurality of memory cell units arranged in parallel with each other in a row direction, each of the memory cell unit comprising: a plurality of memory cell transistors arranged in a column line; a first select gate transistor connected to the bit line at a first end of each of the memory cell transistors; a second select gate transistor connected to the source line at a second end of each of the memory cell transistors so that the memory cell transistors arranged in a row can be connected to the common control gate line; and a select gate line connected to gates of the first select gate transistors arranged in the same row; and a control gate line drive circuit configured to simultaneously write-in all of the memory cell transistors connected to a selected control gate line, wherein a first voltage for transferring a bit line voltage which does not go below a value of a threshold voltage is applied to the select gate line of the first select gate transistor; a second voltage smaller than the first voltage is applied to the select gate line of the first select gate transistor; different types of voltages incapable for write-in is applied at least once to at least a part or all of the control gate lines; and a high plus voltage is applied for write-in to the selected control gate line, once the first voltage is applied, the second voltage, and the different types of voltages are applied before applying the high plus voltage.

17. The nonvolatile semiconductor memory of claim 16 , wherein a predetermined low channel voltage applied for a selected memory cell transistor in a selected memory cell unit to perform write-in by the control gate line drive circuit, when a high plus voltage is applied to the selected control gate line; and a voltage self-boosted from the channel voltage for an unselected memory transistor to restrict write-in by the control gate line drive circuit, the unselected memory transistor is connected to the selected control gate line, through capacitive coupling to one to a plurality of control gate lines.

18. The nonvolatile semiconductor memory of claim 17 , wherein a reference voltage applied to the control gate line to which the different types of voltages have been applied, once the different types of voltages incapable for write-in are applied.

19. The nonvolatile semiconductor memory of claim 18 , wherein, when sequentially writing to all control gate lines in the selected memory cell block, write-in is performed by selecting in order from a first control gate line from the source line side towards the bit line side.

20. The nonvolatile semiconductor memory of claim 19 , wherein a single type of voltage incapable for write-in is provided.

21. The nonvolatile semiconductor memory of claim 20 , wherein a time necessary for applying the voltage incapable for write-in varies depending on the control gate line.

22. The nonvolatile semiconductor memory of claim 21 , wherein the time necessary for applying the voltage incapable for write-in to an unselected control gate line is shorter than time necessary for applying the voltage incapable for write-in to the selected control gate line.

23. The nonvolatile semiconductor memory of claim 21 , wherein the time necessary for applying the voltage incapable for write-in to an unselected control gate line, which is arranged on the bit line side, is shorter than time necessary for applying the voltage incapable for write-in to the selected control gate line and an unselected control gate line, which is arranged further along the source line side than the selected control gate line.