Precharge control circuit of pseudo SRAM

1. A precharge control circuit of a pseudo SRAM, comprising: a precharge set signal generation unit configured to output a precharge set signal; a precharge standby signal generation unit configured to output a precharge standby signal; a precharge signal output unit configured to output a precharge signal in response to the precharge set signal and the precharge standby signal; a first precharge control unit configured to forcedly control the output signal of the precharge standby signal generation unit such that the precharge signal is generated in a period where a chip select signal is disabled, in the case where the chip select signal is disabled long for a first time; and a second precharge control unit configured to forcedly control the output signal of the precharge standby signal generation unit such that the precharge signal is generated in a period where the chip select signal is disabled, in the case where the chip select signal is disabled long for a second time longer than the first time, wherein the precharge signal is generated in response to the operation of the first precharge control unit or the second precharge control unit.

2. The precharge control circuit as claimed in claim 1 , wherein in a period where the first precharge control unit operates, the second precharge control unit is provided not to operate, and in a period where the second precharge control unit operates, the first precharge control unit is provided not to operate.

3. The precharge control circuit as claimed in claim 1 , wherein the first precharge control unit is configured to control the output signal of the precharge standby signal generation unit in response to a sense delay signal and a chip non-select signal, wherein the sense delay signal comprises a signal informing a time point where precharge is performed after the operation of a bit line sense amplifier is completed, and the chip non-select signal comprises a signal that becomes a high level when the chip select signal becomes a high level, and becomes a low level when the chip select signal becomes a low level.

4. The precharge control circuit as claimed in claim 3 , wherein the first precharge control unit comprises: a low pulse generator configured to generate a low pulse when the sense delay signal transits to a high level; a first inverter configured to invert the output signal of the low pulse generator; a NAND gate configured to logically combine an output signal of the first inverter and the chip non-select signal; a second inverter configured to invert an output signal of the NAND gate; and a NMOS transistor controlled according to the output signal of the second inverter and connected between a ground voltage terminal and one node of the precharge standby signal generation unit, which comprises a voltage level opposite to that of the precharge standby signal.

5. The precharge control circuit as claimed in claim 1 , wherein the second precharge control unit is configured to control the output signal of the precharge standby signal generation unit in response to a chip select internal signal and an active signal, wherein the chip select internal signal comprises a signal that becomes a low level when the chip select signal becomes a high level, and becomes a high level when the chip select signal becomes a low level, and the active signal comprises a signal that becomes a high level if a pulse signal informing that predecoding has started is generated, and becomes a low level if the precharge signal is generated.

6. The precharge control circuit as claimed in claim 5 , wherein the second precharge control unit comprises: a low pulse generator configured to generate a low pulse when the sense delay signal transits to a high level; a first inverter configured to invert the output signal of the low pulse generator; a NAND gate configured to logically combine an output signal of the first inverter and the active signal; a second inverter configured to invert an output signal of the NAND gate; and a NMOS transistor controlled according to the output signal of the second inverter and connected between a ground voltage terminal and one node of the precharge standby signal generation unit, which comprises a voltage level opposite to that of the precharge standby signal.

7. The precharge control circuit as claimed in claim 1 , wherein the precharge standby signal generation unit is configured to output the precharge standby signal in response to a reset signal, an active signal and a chip non-select signal, wherein the reset signal comprises a signal that has an opposite phase to that of the precharge signal and is delayed by a delay unit, the active signal comprises a signal that becomes a high level if a pulse signal informing that predecoding has started, and becomes a low level if the precharge signal is generated, and the chip non-select signal comprises a signal that becomes a high level when the chip select signal becomes a high level, and becomes a low level when the chip select signal becomes a low level.

8. The precharge control circuit as claimed in claim 7 , wherein the precharge standby signal generation unit comprises: a PMOS transistor controlled according to a reset signal and connected between a power supply voltage terminal and a first node; a NAND gate configured to logically combine the reset signal and the active signal; a first inverter configured to invert an output signal of the NAND gate; a first NMOS transistor controlled according to an output signal of the first inverter and connected between the first node and a second node; a low pulse generator configured to output a low pulse when the chip non-select signal transits to a high level; a second inverter configured to invert the output of the low pulse generator; a second NMOS transistor controlled according to the output signal of the second inverter and connected between the second node and a ground voltage terminal; and a latch configured to latch a voltage level of the first node and configured to output a precharge standby signal.

9. The precharge control circuit as claimed in claim 8 , wherein the latch comprises an inverter latch having inverters, and is configured to output the precharge standby signal.

10. The precharge control circuit as claimed in claim 1 , wherein the precharge set signal generation unit is configured to output the precharge set signal in response to a sense delay signal and a reset signal, wherein the sense delay signal is a signal informing a time point where precharge is performed after the operation of the bit line sense amplifier is completed, and the reset signal is a signal comprising an opposite phase to that of the precharge signal and is delayed by the delay unit.

11. The precharge control circuit as claimed in claim 10 , wherein the precharge set signal generation unit comprises: a PMOS transistor controlled according to the reset signal and connected between a power supply voltage terminal and a node; a low pulse generator configured to output a low pulse when the sense delay signal transits to a high level; an inverter configured to invert the output of the low pulse generator; a NMOS transistor controlled according to the output signal of the inverter and connected between the node and a ground voltage terminal; and a latch configured to invert a voltage level of the node and configured to output a precharge set signal.

12. The precharge control circuit as claimed in claim 11 , wherein the latch comprises an inverter latch having inverters, and is configured to output the precharge set signal.

13. The precharge control circuit as claimed in claim 11 , wherein the precharge signal output unit comprises: a NAND gate configured to logically combine the precharge set signal and the precharge standby signal; an inverter configured to invert the output signal of the NAND gate, and configured to output a precharge signal; and a delay unit configured to delay the output signal of the NAND gate for a predetermined time, and configured to output a reset signal.