Parallel architecture digital filter and spread spectrum signal receiver using such a filter

1. A parallel architecture digital filter receiving p input signals (I 0 , . . . , I i , . . . . I p−1 ) and delivering p output signals (S 0 , . . . , S 1 , . . . , S p−1 ) which are the sums of the input signals weighted with M coefficients (C 0 , C 1 , . . . , C M−1 ), this filter comprising p parallel channels (V 0 , . . . , V i , . . . , V p−1 ) receiving the input signals (I 0 , . . . , I i , . . . , I p−1 ), characterized in that it comprises r+1 stages (E 0 , . . . , E j , . . . , E r ), where r is the integer portion of ratio (M+p−2)/2, the stage of rank j delivering p intermediate signals (R 0 j , . . . R 1 j , . . . R p−1 ) which are the weighted sums of the input signals defined by: R i j = ∑ q = 0 p - 1 ⁢ ⁢ ( C M - 1 - q + i - jp ) ⁢ I q + jp the filter further comprising a summing means receiving said intermediate signals (R i j ) and delivering p sums defined by: S i = ∑ j = 0 r ⁢ ⁢ R i j these p sums forming p output signals (S 0 , . . . , S i , . . . S p−1 ).

2. The digital filter according to claim 1 , wherein the number of channels p is equal to 2, the filter then comprising a first channel with first storing means (R p ) for storing samples of the input signals of even rank (I k p , I k−1 pi , . . . ) and a second channel with second storing means (R i ) for storing the samples of the input signals of odd rank (I k p , I k−1 i , . . . ), and further comprising first (M 0 p , . . . , M 1 p , . . . ADD p ) and second (M 0 i , . . . , M 1 i , . . . , ADD i ) means, for respectively calculating even (S k p ) and odd (S k i ) weighted sums.

3. The filter according to claim 2 , wherein the first and the second means for calculating the even and odd weighted sums each comprise multipliers (M 1 p , M 3 p , . . . , M 0 i , M 2 i . . . ) each receiving a respective sample of the input signals (I k−1 p , I k p , . . . , I k−1 i , I k i . . . ) and a respective weighting coefficient (C 1 , C 3 , C 0 , C 2 ) (C 0 , C 2 , C 1 , C 3 ), and an adder (ADD i , ADD p ) connected to the multipliers.

4. The filter according to claim 2 , wherein the first and the second storing means comprises a first (R p ) and a second (R i ) shift register, respectively.

5. The filter according to claim 4 , wherein each shift register (R p , R i ) comprises cells (B p ) (B i ) arranged in series, each cell consisting of a flip-flop with an input (D) and a direct output (Q), wherein the input of a flip-flop of rank k is connected to the direct output (Q) of the flip-flop of rank k-I and the direct output (Q) of the flip-flop of rank k is connected to the input of the flip-flop of rank k+1, each flip-flop further comprising a complemented output (!Q), each of the multipliers being a multiplexers (MPX p ) (MPX i ) with two inputs connected to the direct (Q) and complemented (!Q) outputs of the flip-flops, respectively, each multiplexer further comprising a control input receiving a positive or negative control signal (C 0 , C 1 , . . . , C m−1 ) and an output, which is connected to a one of the two inputs according to the sign of the control signal.

6. A receiver for direct sequence spread spectrum signals comprising: at least an analog/digital converter (CAN(I), CAN(Q)) receiving a spread spectrum signal and delivering digital samples of this signal, at least a digital filter (F(I), F(Q)) with coefficients (C j ) adapted to a spread spectrum sequence, this filter receiving the digital samples delivered by the analog/digital converter and delivering a filtered signal, means (DD, Inf/H, D) for processing the filtered signal to restore transmitted data (d), this receiver being characterized in that the digital filter (F(I), F(Q)) is a parallel architecture digital filter according to claim 1 .

7. The receiver according to claim 6 , comprising first and second channels in parallel, the first (I) for processing a signal in phase with a carrier and the second (Q) for processing a signal in phase quadrature with said carrier, each channel comprising a respective parallel architecture digital filter (F(I), F(Q)) with, for the first channel (I), notably, first and second adders (ADD(I) p , ADD(I) i ) delivering first and second weighted sums (S(I) k p , S(I) k i ) and, for the second channel (Q), notably, first and second adders (ADD(Q) p , ADD(Q) i ) delivering first and second weighted sums (S(Q) k p , S(Q) k i ).

8. The receiver according to claim 7 , wherein the first channel (I) comprises a first differential demodulation circuit (DD(I)) and the second channel (Q) comprises a second differential demodulation circuit (DD(Q)), the first differential demodulation circuit (DD(I)) receiving the first weighted sums (S(I) k p , S(Q) k p ) delivered by the respective parallel architecture digital filters (F(I), F(Q)) of the first and second channels (I), (Q), and delivering a first DOT and a first CROSS signal (DOT p , CROSS p ), the second differential demodulation circuit (DD(Q)) receiving the second weighted sums (S(I) k i ) and (S(Q) k i ) delivered by the respective parallel architecture digital filters (F(I), F(Q)) of the first and second channels (I, Q) and delivering a second DOT and a second CROSS signal (DOT i , CROSS i ).

9. The receiver according to claim 8 , comprising a clock and an information circuit (Inf/H) receiving each of the first and second DOT and CROSS signals (DOT p , CROSS p ), (DOT i , CROSS i ) delivered by the first and second differential demodulation circuits (DD(I), DD(Q)) and delivering even and odd information signals (S inf p , S inf i ), a clock signal (SH) and a parity signal (Sp/i).

10. A receiver for direct sequence spread spectrum signals comprising: at least an analog/digital converter (CAN(I), CAN(Q)) receiving a spread spectrum signal and delivering digital samples of this signal, at least a digital filter (F(I), F(Q)) with coefficients (C j ) adapted to the spread spectrum sequence, this filter receiving the samples delivered by the digital/analog converter and delivering a filtered signal, means (DD, Inf/H, D) for processing the filtered signal able to restore the transmitted data (d), this receiver being characterized in that the digital filter (F(I), F(Q)) is a parallel architecture digital filter according to claim 5 .