A method of producing a multilayer wiring substrate is disclosed. The multilayer wiring substrate is free from a core substrate and includes a build up layer which includes an insulator layer and a wiring layer. One of a first main surface and a second main surface of the build up layer is formed with a metal supporting frame body. The method includes the steps of: forming a first insulator layer on a first main surface of a metal supporting plate, where the first insulator layer is included in the insulator layer and becomes a first resist layer which is positioned on the first main surface's side of the build up layer, and forming a first metal pad layer in a given position on a first main surface of the first insulator layer, where the first metal pad layer is included in the wiring layer and becomes a metal pad layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of producing a multilayer wiring substrate, the multilayer wiring substrate being free from a core substrate and comprising a build up layer which comprises an insulator layer and a wiring layer, one of a first main surface and a second main surface of the build up layer being formed with a metal supporting frame body, the method comprising the following steps of: i) forming a first insulator layer substantially on a first main surface of a metal supporting plate, the first insulator layer being included in the insulator layer and positioned on the first main surface's side of the build up layer, ii) forming a first metal pad layer in a given position on a first main surface of the first insulator layer, the first metal pad layer being included in the wiring layer, and iii) removing at least a portion of the metal supporting plate underlying the first insulator layer, to form said metal supporting frame body.
2. The method of producing the multilayer wiring substrate, as claimed in claim 1 , wherein said removing comprises: subjecting the metal supporting plate to an etching step for carrying out an etching treatment, and using the first insulator layer as an etch stop layer.
3. The method of producing the multilayer wiring substrate, as claimed in claim 2 , wherein a remnant of the metal supporting plate after the etching step is free from striding over an area below the first metal pad layer, the area being defined as a projected area from a thick part of the first metal pad layer substantially downward.
4. The method of producing the multilayer wiring substrate, as claimed in claim 1 , wherein the method further comprises a first opening step of: subjecting the first insulator layer to an opening treatment, and opening a given position of the first insulator layer in such a manner that a main surface on the first insulator layer's side of the first metal pad layer includes a coated region coated with the first insulator layer and an exposed region having an exposed surface.
5. The method of producing the multilayer wiring substrate, as claimed in claim 4 , wherein the first opening step uses a dry etching.
6. The method of producing the multilayer wiring substrate, as claimed in claim 5 , wherein the dry etching of the first opening step is a laser machining.
7. The method of producing the multilayer wiring substrate, as claimed in claim 4 , wherein the method further comprises the following steps of: i) forming a second insulator layer included in the insulator layer and which is positioned on the second main surface's side of the build up layer opposite to the first main surface's side of the build up layer, ii) forming, prior to the forming step of forming the second insulator layer, a second metal pad layer substantially beneath the second insulator layer, the second metal pad layer being included in the wiring layer, and iii) a second opening step of; subjecting the second insulator layer to an opening treatment, and opening a given position of the second insulator layer in such a manner that a main surface on the second insulator layer's side of the second metal pad layer includes a coated region coated with the second insulator layer and an exposed region having an exposed surface.
8. The method of producing the multilayer wiring substrate, as claimed in claim 7 , wherein the exposed region of the first metal pad layer formed through the first opening step is smaller than the exposed region of the second metal pad layer formed through the second opening step, and the first opening step uses a dry etching.
9. The method of producing the multilayer wiring substrate, as claimed in claim 8 , wherein the dry etching of the first opening step is a laser machining.
10. The method of producing the multilayer wiring substrate, as claimed in claim 8 , wherein the main surface on the first insulator layer's side of the first metal pad layer is in a range from 2,800 μm 2 to 32,000 μm 2 , and the exposed region of the first metal pad layer exposed after the first opening step is in a range from 1,900 μm 2 to 26,000 μm 2 .
11. The method of producing the multilayer wiring substrate, as claimed in claim 8 , wherein the main surface on the second insulator layer's side of the second metal pad layer is in a range from 49,000 μm 2 to 600,000 μm 2 , and the exposed region of the second metal pad layer exposed after the second opening step is in a range from 30,000 μm 2 to 400,000 μm 2 .
12. The method of producing the multilayer wiring substrate, as claimed in claim 8 , wherein when being shaped substantially into a circle, the main surface on the first insulator layer's side of the first metal pad layer has a diameter in a range from 60 μm to 200 μm, and when being shaped substantially into a circle, the exposed region of the first metal pad layer has a diameter in a range from 50 μm to 180 μm.
13. The method of producing the multilayer wiring substrate, as claimed in claim 8 , wherein when being shaped substantially into a circle, the main surface on the second insulator layer's side of the second metal pad layer has a diameter in a range from 250 μm to 870 μm, and when being shaped substantially into a circle, the exposed region of the second metal pad layer has a diameter in a range from 200 μm to 710 μm.
14. The method of producing the multilayer wiring substrate, as claimed in claim 1 , wherein the forming step of forming the first insulator and the forming step of forming the first metal pad layer are sequentially carried out.
15. A multilayer wiring substrate free from a core substrate, comprising: a build up layer and a metal supporting frame body having a void space, said metal supporting frame body supporting one of a first main surface and a second main surface of the build up layer, the build up layer comprising; i) a first insulator layer formed substantially on a first main surface of the metal supporting frame body, the first insulator layer being positioned on the first main surface's side of the build up layer, ii) a first metal pad layer formed in a given position on a first main surface of the first insulator layer, (iii) a second insulator layer positioned on the second main surface's side of the build up layer opposite to the first main surface's side of the build up layer; and (iv) a second metal pad layer formed substantially beneath the second insulator layer.
16. The multilayer wiring substrate, as claimed in claim 15 , wherein a main surface on the first insulator layer's side of the first metal pad layer is in a range from 2,800 μm 2 to 32,000 μm 2 , and an exposed region of the first metal pad layer exposed after a first opening step is in a range from 1,900 μm 2 to 26,000 μm 2 .
17. The multilayer wiring substrate, as claimed in claim 15 , wherein a main surface on the second insulator layer's side of the second metal pad layer is in a range from 49,000 μm 2 to 600,000 μm 2 , and an exposed region of the second metal pad layer exposed after a second opening step is in a range from 30,000 μm 2 to 400,000 μm 2 .
18. The multilayer wiring substrate, as claimed in claim 15 , wherein when being shaped substantially into a circle, a main surface on the first insulator layer's side of the first metal pad layer has a diameter in a range from 60 μm to 200 μm, when being shaped substantially into a circle, an exposed region of the first metal pad layer has a diameter in a range from 50 μm to 180 μm, when being shaped substantially into a circle, a main surface on the second insulator layer's side of the second metal pad layer has a diameter in a range from 250 μm to 870 μm, and when being shaped substantially into a circle, an exposed region of the second metal pad layer has a diameter in a range from 200 μm to 710 μm.
19. A method of producing a multilayer wiring substrate comprising: forming a first insulator layer on a side of a metal supporting plate; forming a plurality of metal layers and a plurality of insulator layers alternatively on the first insulator layer, being as build up layers; removing at least a portion of the metal supporting plate underlying the first insulator layer to expose the first insulator layer; forming a first opening in the first insulator layer to expose a first metal pad being in a bottom metal layer of the plurality of metal layers, and forming a second opening in a top insulator layer of the plurality of insulator layers to expose a second metal pad being in a top metal layer of the plurality of metal layers.
20. The method of producing a multilayer wiring substrate, as claimed in claim 19 , further comprising: forming a metal supporting frame body on the top insulator layer of the plurality of insulator layers.
21. A multilayer wiring substrate comprising: first and third levels of a metal layer, each of said first and third levels of the metal layer being defined by first and second surfaces opposing to each other and third and fourth surfaces opposing to each other; a first insulator layer intervening between said first and third levels of the metal layer, said first level of the metal layer being partially embedded in said first insulator layer such that the second, third and fourth surfaces of said first level of the metal layer are in contact with said first insulator layer while the first surface of said first level of the metal layer forms a substantially flat plane with a surface of said first insulator layer, said third level of the metal layer being formed on said first insulator layer such that the first surface of said third level of the metal layer is in contact with the first insulator layer and the second, third and fourth surfaces of said third level of the metal layer are free from being in contact with the first insulator layer; a second level of a metal layer embedded into said first insulator layer between said first and third levels of the metal layer; a second insulator layer formed to cover said substantially flat plane, said second insulator layer having a first opening to expose a part of the first surface of said first level of the metal layer, said part of the first surface of said first level of the metal layer thereby forming a first metal pad; a third insulator layer formed to cover the second, third and fourth surfaces of said third level of the metal layer and a part of said first insulator layer, said third insulator layer having a second opening to expose a part of the second surface of said third level of the metal layer, said part of the second surface of said third level of the metal layer thereby forming a second metal pad; and a supporting frame body formed on said third insulator layer; said supporting frame having a space in which a semiconductor chip, which has an electrode that is to be electrically connected to said second metal pad, is accommodated.
22. The multilayer wiring substrate, as claimed in claim 21 , wherein a first region in which said first metal pad is formed and a second region in which said second metal pad is formed are overlapped.
23. The multilayer wiring substrate, as claimed in claim 21 , wherein said first opening is in a range from 30,000 μm 2 to 400,000 μm 2 .
24. The multilayer wiring substrate, as claimed in claim 21 , wherein said second opening is in a range from 1,900 μm 2 to 26,000 μm 2 .
25. A method of producing a multilayer wiring substrate comprising: forming an insulating layer on a supporting plate; piling on said insulating layer a plurality of levels of a metal layer and a plurality of levels of an insulator layer alternately to form a build-up layer; selectively forming an opening in a top one of said levels of the insulating layer to expose a part of a top one of said levels of the metal layers, said part thereby forming a metal pad; removing said supporting plate so that said insulating layer is exposed; and forming a supporting frame body on said top one of said levels the insulator layers.
26. The method of producing the multilayer wiring substrate, as claimed in claim 25 , further comprising: selectively forming another opening in said insulating layer to expose a part of a bottom one of said levels of the metal layers, said part thereby forming another metal pad.
27. The method of producing the multilayer wiring substrate, as claimed in claim 26 , wherein said forming another opening in said insulating layer is formed by dry etching.
28. The method of producing the multilayer wiring substrate, as claimed in claim 27 , wherein said dry etching is a laser machining.
29. The method of producing the multilayer wiring substrate, as claimed in claim 26 , wherein said opening in said top one of said levels of the insulating layer is smaller than said another opening in said insulator layer.
30. The method of producing the multilayer wiring substrate, as claimed in claim 25 , wherein said removing comprises: subjecting said supporting plate to an etching step for carrying out an etching treatment, and using said insulator layer as an etch stop layer.
31. The method of producing the multilayer wiring substrate, as claimed in claim 25 , wherein said forming said opening in said top one of said levels of the insulating layer is formed by dry etching.
32. The method of producing the multilayer wiring substrate, as claimed in claim 31 , wherein said dry etching is a laser machining.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 5, 2003
June 13, 2006
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