A semiconductor device including an N-type semiconductor substrate which includes arsenic as an impurity, a first electrode formed on a main surface of the N-type semiconductor substrate, a ground surface formed on another surface of the N-type semiconductor substrate, a second electrode formed on the ground surface and ohmically-contacted with the N-type semiconductor substrate, a semiconductor element formed in the N-type semiconductor substrate and flowing current between the first electrode and the second electrode during On-state thereof. The device has a reduced ON-resistance thereof.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of manufacturing a vertical type semiconductor device comprising: preparing a semiconductor wafer which has an arsenic doped silicon substrate doped at an impurity concentration of between 7×10 18 –1×10 21 cm −3 and a semiconductor layer disposed over the silicon substrate; forming a semiconductor element at a surface portion of said semiconductor layer; forming a first metal layer for a first electrode of said semiconductor element over said surface portion of said semiconductor layer grinding a back of said silicon substrate to thin said silicon substrate and roughen a back surface of said silicon substrate; forming on said roughened back surface a second metal layer for a second electrode of said semiconductor element; and packaging by molding technique a chip with said semiconductor element formed therein.
2. A method of claim 1 , further comprising, prior to said packaging, wire-bonding between said first metal layer and a lead-frame.
3. A method of claim 1 , wherein said grinding includes thinning said silicon substrate until a thickness from a surface of said first metal layer to said back surface is 200–450 microns.
4. A method of claim 2 , wherein said grinding includes thinning said silicon substrate until a thickness from a surface of said first metal layer to said back surface is 200–450 microns.
5. A method of claim 1 , wherein said second metal layer comprises a metal selected from the group consisting of titanium (Ti), vanadium (V), chromium (Cr) and nickel (Ni).
6. A method of claim 1 , wherein said grinding includes roughening said back surface of said silicon substrate to have a surface roughness of between 0.2–0.6 microns.
7. A method of claim 1 , wherein said semiconductor element includes a MOSFET formed at said surface portion of said semiconductor layer, said first electrode being a source electrode of said MOSFET, and said second electrode being a drain electrode of said MOSFET.
8. A method of claim 2 , wherein said semiconductor element includes a MOSFET formed at said surface portion of said semiconductor layer, said first electrode being a source electrode of said MOSFET, and said second electrode being a drain electrode of said MOSFET.
9. A method of claim 3 , wherein said semiconductor element includes a MOSFET formed at said surface portion of said semiconductor layer, said first electrode being a source electrode of said MOSFET, and said second electrode being a drain electrode of said MOSFET.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 29, 2004
June 20, 2006
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