A process for etching a sacrificial layer of a structure. The structure is exposed to a plasma derived from nitrogen trifluoride for etching the sacrificial layer. The process is selective in that it etches titanium-nitride and titanium but does not affect adjacent silicon dioxide or aluminum layers. Applications of the process include the formation of integrated circuit structures and MEMS structures.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A process for selectively etching a material layer formed in a structure, comprising: forming a plasma from a fluorine-containing gas; maintaining the structure temperature at greater than about 100° C.; forming an opening extending from a surface of the structure to at least the material layer, wherein the material layer is exposed on a sidewall of the opening; exposing the material layer to the plasma through the opening; and etching the material layer by allowing plasma to contact the material layer through the opening for removing at least a portion of the material layer that is exposed on the sidewall of the opening, wherein any material remaining after the etching step is laterally disposed relative to the opening, wherein the material layer is selected from among titanium, titanium-nitride, a titanium compound and a titanium alloy.
2. The process of claim 1 wherein the fluorine-containing gas comprises NF 3 .
3. The process of claim 1 wherein the opening is selected from among a substantially vertical via opening and a substantially horizontal trench opening.
4. The process of claim 1 wherein the opening exhibits a relatively high aspect ratio of at least about 50:1.
5. The process of claim 1 wherein the step of exposing further comprises adjusting an exposure duration to control an extent of the material layer etch.
6. The process of claim 1 wherein the material layer comprises a sacrificial layer.
7. The process of claim 1 wherein the structure comprises layers selected from among silicon dioxide, polycrystalline silicon, amorphous silicon, single-crystal silicon, silicon nitride, tungsten, elemental aluminum and aluminum alloys.
8. The process of claim 1 wherein the step of maintaining the structure temperature further comprises maintaining the structure temperature between about 100° C. and 200° C.
9. The process of claim 1 wherein the structure comprises an overlying and an underlying layer with the material layer disposed therebetween, and wherein the material layer comprises a sacrificial layer, and wherein after the exposing step the overlying and the underlying layers are decoupled.
10. The process of claim 1 wherein the structure comprises an overlying and an underlying layer, and wherein the material layer comprises a sacrificial layer, and wherein after the exposing step one or more regions of the material layer are removed.
11. The process of claim 1 wherein the step of forming the plasma further comprises forming the plasma at a sub-atmospheric pressure in the range of about 500 mT to about 50,000 mT.
12. A process for selectively etching a sacrificial layer formed in a structure comprising a microelectromechanical device and one or more semiconductor devices, the process comprising; forming a plasma etchant from a fluorine-containing gas; maintaining the structure temperature at greater than about 100° C.; forming an opening extending from a surface of the structure to the sacrificial layer, wherein the sacrificial layer is exposed on a sidewall of the opening; and exposing the sacrificial layer to the plasma etchant through the opening for removing regions of the sacrificial layer without compromising the integrity of the semiconductor devices, wherein at least a portion of the sacrificial layer material that is exposed on the sidewall of the opening is removed and any remaining sacrificial layer material is laterally disposed relative to the opening, wherein the sacrificial layer is selected from among titanium, titanium-nitride, a titanium compound and a titanium alloy.
13. The process of claim 12 wherein the opening exhibits a relatively high aspect ratio of at least 50:1.
14. The process of claim 12 wherein the step of maintaining the structure temperature further comprises maintaining the structure temperature between about 100° C. and 200° C.
15. The process of claim 12 wherein the micromechanical device comprises an overlying and an underlying layer with the material layer disposed therebetween and wherein the material layer comprises a sacrificial layer, and wherein after the exposing step the overlying and the underlying layers are decoupled.
16. A process for selectively etching a sacrificial layer formed in a structure comprising a microelectromechanical device and one or more semiconductor devices, the process comprising: forming a plasma etchant from a fluorine-containing gas; maintaining the structure temperature at greater than about 100° C.; forming an opening extending from a surface of the structure to the sacrificial layer; exposing the sacrificial layer to the plasma etchant to remove regions of the sacrificial layer without compromising the integrity of the semiconductor devices, wherein at least a portion of removed regions of the sacrificial layer are laterally disposed relative to the opening and wherein an etch ratio of the etchant is at least 10:1 wherein the sacrificial layer is selected from among titanium, titanium-nitride, a titanium compound and a titanium alloy.
17. The process of claim 16 wherein the microelectromechanical device comprises in stacked relation first, second and third material layers and wherein the second material layer comprises and is selected from among titanium, titanium-nitride and a titanium alloy.
18. The process of claim 17 wherein the first and the third material layers are selected from among silicon dioxide, polycrystalline silicon, amorphous silicon, single-crystal silicon, silicon nitride, tungsten, elemental aluminum and aluminum alloys.
19. A process for forming a contact between a conductive via and a doped region formed in a semiconductor substrate, comprising: forming a sacrificial layer overlying the doped region; forming a material layer overlying the sacrificial layer; forming an opening in the material layer, wherein the opening exposes a region of the sacrificial layer; etching at least a portion of the sacrificial layer disposed laterally with respect to the opening; forming a conductive material in the etched portion of the sacrificial layer; and forming conductive material in the opening.
20. The process of claim 19 wherein the step of etching further comprises: forming a plasma from a fluorine-containing gas; maintaining the substrate temperature at greater than about 100° C.; and exposing the sacrificial layer to the plasma to etch the sacrificial layer.
21. The process of claim 20 wherein the step of exposing further comprises exposing the sacrificial layer to the plasma through the opening.
22. The process of claim 19 wherein the opening exhibits a relatively high aspect ratio of at least about 50:1.
23. A process for forming a reentrant feature in a substrate, comprising: forming the substrate comprising in stacked relation, a first material layer, a first sacrificial layer, a second material layer, a second sacrificial layer, and a third material layer; forming a substantially vertical region of sacrificial material in the second material layer bridging the first and the second sacrificial layers; forming an opening through the third material layer, the second sacrificial layer and the second material layer, wherein the opening is bounded by the bridging sacrificial material and exposes the first sacrificial layer; laterally etching by plasma containing fluorine-containing gas a portion of the first and the second sacrificial layers proximate the opening and vertically etching the bridging sacrificial material.
24. The process of claim 23 wherein the step of etching further comprises exposing the substrate to a fluorine-containing gas.
25. The process of claim 23 wherein the opening exhibits a relatively high aspect ratio of at least about 50:1.
26. The process of claim 23 wherein the material of the first and the second sacrificial layers and the bridging sacrificial layer is selected from among titanium, titanium-nitride, a titanium compound and a titanium alloy.
27. The process of claim 23 wherein the material of the first, second and third material layers is selected from among silicon dioxide, polycrystalline silicon, amorphous silicon, single-crystal silicon, silicon nitride, tungsten, elemental aluminum and aluminum alloys.
28. The process of claim 23 wherein the etching step further comprises maintaining the substrate between about 100° C. and 200° C.
29. The process of claim 23 wherein the first material layer comprises a dielectric material layer, the process further comprising; forming a first capacitor plate in an etched region of the first sacrificial layer; and forming a second capacitor plate underlying the first material layer, wherein the dielectric material layer intermediate the first and the second capacitor plates comprises a capacitor dielectric.
30. The process of claim 23 wherein the second material layer comprises a dielectric material layer, the process further comprising; forming a first capacitor plate in an etched region of the second sacrificial layer; and forming a second capacitor plate overlying the third material layer, wherein the dielectric material layer intermediate the first and the second capacitor plates comprises a capacitor dielectric.
31. The process of claim 23 wherein the second material layer comprises first and second portions separated by the opening, and wherein the second material layer comprises a conductive material layer, arid wherein the first and the second portions operate as first and second capacitor plates, and wherein a capacitor dielectric comprises a region from which the bridging sacrificial material has been etched.
32. The process of claim 31 further comprising forming a dielectric material in the region from which the bridging sacrificial material has been etched, wherein a capacitance of the capacitor is responsive to the dielectric material.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 30, 2003
July 18, 2006
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