Semiconductor integrated circuit device and test method thereof

1. A semiconductor integrated circuit device comprising: a test target circuit including a plurality of nodes and terminals; a control circuit configured to generate an internal reset signal, and an internal operation mode signal, in response to an external clock signal or an internal clock signal generated from the external clock signal, an external reset signal, and an external operation mode signal inputted therein; and an observation circuit configured to receive input data from observation points of the test target circuit through branches to the observation circuit, in order to observe a test that causes the test target circuit to perform a substantially normal functional operation, the observation points having been selected from the nodes and terminals corresponding to faults not detected by a fault simulation that causes the test target circuit to perform a substantially normal functional operation, the observation circuit comprising a plurality of flip-flops, wherein the observation circuit is controlled by the internal clock signal, the internal reset signal, and the internal operation mode signal, and is configured to reset the flip-flops in response to the internal reset signal, and to selectively perform, using the flip-flops, (a) a first operation of compressing input data from the observation points to generate a signature during substantially normal operation of the test target circuit, the input data being generated in the test target circuit in accordance with test patterns that cause the test target circuit to perform a substantially normal functional operation, and (b) a second operation of serially transferring data, to cause the flip-flops to be connected in series and to read the signature out of the observation circuit, in response to the internal operation mode signal.

2. A device according to claim 1 , wherein a node or terminal selected as one of the observation points corresponds to an undetected fault obtained by the fault simulation and to a node name in circuit connection information at RT (Register Transfer) or higher level.

3. A device according to claim 1 , wherein the observation points are divided into groups on the basis of periods of time necessary for data at each of the observation points to take a settled value after the external reset signal is inputted, the observation circuit comprises observation circuits provided respectively to the groups of the observation points, and the control circuit supplies internal reset signals respectively to the observation circuits of the groups.

4. A device according to claim 1 , wherein the control circuit includes a control logic, which generates the internal reset signal, and resets the observation circuit, using a serial operation.

5. A device according to claim 1 , wherein the observation circuit is arranged to forcibly cause input data from a specific one of the observation points to be invalid and to be a fixed value.

6. A device according to claim 1 , wherein the observation points are respectively in synchronism with different clock signals, and are divided into groups, each of which observation points having the same clock signal belonging to one of the groups, and the observation circuit comprises observation circuits provided respectively to the groups of the observation points, and each of the observation circuits is operated by an internal clock signal that is the same as a clock signal with which a corresponding one of the groups of the observation points is in synchronism.

7. A device according to claim 6 , wherein at least one of the observation points is connected to one of the observation circuits, which is operated in synchronism with an internal clock signal different from a clock signal with which said at least one of the observation points is in synchronism.

8. A device according to claim 1 , wherein data at each of the observation points is selectively inputted into the observation circuit in accordance with the test pattern.

9. A device according to claim 1 , wherein the observation circuit comprises: the flip-flops provided in association with the observation points; a first XOR gate circuit configured to subject outputs of predetermined ones of the flip-flops to an exclusive OR operation; a multiplexer configured to subject a serial input data and an output of the first XOR gate circuit to a selection operation on the basis of the internal operation mode signal; a plurality of AND gates disposed respectively to the flip-flops, and configured to subject respective outputs of the observation points and the internal operation mode signal to an AND operation; and a plurality of second XOR gates disposed respectively to the flip-flops, and configured to subject respective outputs of the AND gates and respective specific outputs to an exclusive OR operation, the specific output of a first stage one of the second XOR gates being an output of the multiplexer, and the specific output of the other of the second XOR gates being an output of a former stage one of the flip-flops.

10. A device according to claim 9 , further comprising a gate configured to selectively output one of a signal, which forcibly causes input data from a corresponding one of the observation points to be invalid, and the internal operation mode signal, to a specific one of the AND gates.

11. A device according to claim 1 , wherein the internal reset signal is generated as part of the internal operation mode signal.