Patentable/Patents/US-7087533
US-7087533

Method for fabricating semiconductor device

PublishedAugust 8, 2006
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A method for fabricating a semiconductor device, wherein a multi-layered hard mask layer having a stacked structure of nitride film/oxide film/nitride film is disclosed. The method for fabricating a semiconductor device comprises the steps of: forming a gate insulating film and a conductive layer for gate electrode; forming a multi-layered hard mask layer on the conductive layer, wherein each layer of the multi-layered hard mask layer is formed of materials different from one another; etching the structure to form a stacked structure of a gate insulating film pattern, a gate electrode and a hard mask layer pattern; forming an insulating film spacer; forming an interlayer insulating film on the entire surface; etching the interlayer insulating film to form a landing plug contact hole; forming a conductive layer for landing plug on the entire surface; and planarizing the conductive layer for a landing plug to form a landing plug.

Patent Claims
1 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A method for fabricating a semiconductor device, comprising the steps of: sequentially forming a gate insulating film and a conductive layer for a gate electrode on a semiconductor substrate; forming a multi-layered hard mask layer on the conductive layer; etching the hard mask layer, the conductive layer and the gate insulting film using a gate electrode mask to form a stacked structure of a gate insulating film pattern, a gate electrode and a hard mask layer pattern serving as a gate pattern; forming an insulating film spacer on a sidewall of the stacked structure; forming an interlayer insulating film on the entire surface; etching the interlayer insulating film using a landing plug contact etching mask to form a landing plug contact hole exposing the semiconductor substrate; forming a conductive layer for a landing plug on the entire surface so as to fill the landing plug contact hole; and planarizing the conductive layer for a landing plug to form a landing plug, wherein the multi-layered hard mask layer includes a stacked structure of nitride film/oxide film/nitride film serving as a barrier layer during the etching process for a gate pattern.

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Patent Metadata

Filing Date

June 30, 2003

Publication Date

August 8, 2006

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