In a system for programming non-volatile storage, technology is disclosed for programming with greater precision and reasonable program times. In one embodiment, a first voltage is applied to a bit line for a first non-volatile storage element in order to inhibit that first non-volatile storage element. A first program voltage is applied to the first non-volatile storage element. For example, a program pulse is applied to a control gate for the first non-volatile storage element. During the program pulse, the bit line is changed from said first voltage to a second voltage, where the second voltage allows the first non-volatile storage element to be programmed.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for programming non-volatile storage, comprising: applying a first program voltage to a plurality of non-volatile storage elements, a first set of said non-volatile storage elements are in a coarse programming mode and a second set of said non-volatile storage elements are in a fine programming mode; providing a programming bit line voltage to bit lines for said first set of non-volatile storage elements during said first program voltage; providing an inhibit bit line voltage to bit lines for said second set of non-volatile storage elements during said first program voltage; and changing said bit lines for said second set of non-volatile storage elements during said first program voltage to allow programming of said second set of non-volatile storage elements.
2. A method according to claim 1 , wherein: said applying a first program voltage includes applying a program pulse on a first word line; and said changing said bit lines includes lowering said bit lines for said second set of non-volatile storage elements from said inhibit bit line voltage to a said programming bit line voltage during said pulse.
3. A method according to claim 1 , wherein: said applying a first program voltage includes applying a program pulse on a first word line; said step of changing said bit lines includes lowering said bit lines for said second set of non-volatile storage elements from said inhibit bit line voltage to a program level at different times during said pulse based on a differential between current threshold voltage levels and target threshold voltage levels.
4. A method according to claim 1 , wherein: said programming bit line voltage is zero volts.
5. A method according to claim 1 , wherein: said changing includes performing one change to said bit lines.
6. A method according to claim 1 , further comprising: applying a pre-charging voltage to said non-volatile storage elements prior to applying said first program voltage.
7. A method according to claim 1 , further comprising: lowering said first program voltage; and raising said first program voltage, said changing said bit lines is performed after lowering said first program voltage and prior to raising said first program voltage.
8. A method according to claim 1 , wherein: said plurality of non-volatile storage elements are flash memory devices.
9. A method according to claim 1 , wherein: said plurality of non-volatile storage elements are multi-state flash memory devices.
10. A method according to claim 1 , wherein: plurality of non-volatile storage elements are NAND flash memory devices.
11. A non-volatile storage system, comprising: a first non-volatile storage element; and a control circuit in communication with said first non-volatile storage element, said control circuit performs a method comprising: applying a first program voltage to a plurality of non-volatile storage elements, a first set of said non-volatile storage elements are in a coarse programming mode and a second set of said non-volatile storage elements are in a fine programming mode, providing a programming bit line voltage to bit lines for said first set of non-volatile storage elements during said first program voltage, providing an inhibit bit line voltage to bit lines for said second set of non-volatile storage elements during said first program voltage, and changing said bit lines for said second set of non-volatile storage elements during said first program voltage to allow programming of said second set of non-volatile storage elements.
12. A non-volatile storage system according to claim 11 , wherein: said applying a first program voltage includes applying a program pulse on a first word line; and said changing said bit lines includes lowering said bit lines for said second set of non-volatile storage elements from said inhibit bit line voltage to said programming bit line voltage during said pulse.
13. A non-volatile storage system according to claim 11 , wherein: said applying a first program voltage includes applying a program pulse on a first word line; and said changing said bit lines is performed during said pulse.
14. A non-volatile storage system according to claim 11 , wherein: said first non-volatile storage element is a NAND multi-state flash memory device.
15. A non-volatile storage system according to claim 11 , wherein: said first non-volatile storage element is a flash memory device.
16. A method for programming non-volatile storage, comprising: determining whether a first non-volatile storage element is in a coarse programming mode or a fine programming mode; applying a first program voltage to a control gate of said first non-volatile storage element; and making a first change to a bit line voltage for said first non-volatile storage element while applying said first program voltage to said control gate if said first non-volatile storage element is in said fine programming mode and not making said first change while applying said first program voltage to said control gate if said first non-volatile storage element is in said coarse programming mode.
17. A method according to claim 16 , wherein: said making said first change includes changing said bit line voltage from a first voltage level to a second voltage level.
18. A method according to claim 16 , wherein: said making said first change includes changing said bit line voltage from an inhibit level to a program level.
19. A method according to claim 16 , wherein: said applying a first program voltage to a control gate includes applying a pulse; and said first change to said bit line voltage is made during said pulse.
20. A method according to claim 19 , wherein: said pulse includes a first portion, a second portion and a third portion; said pulse is at a full magnitude during said first portion and said third portion; said pulse is at a lower magnitude during said second portion; and said change to said bit line is made during said second portion.
21. A method according to claim 16 , wherein said determining whether a first non-volatile storage element is in a coarse programming mode or a fine programming mode comprises: testing whether a threshold voltage of said first non-volatile storage element is above a coarse/fine verify level, said method for programming non-volatile storage is programming said first non-volatile storage element to a target state having a minimum threshold voltage level, said coarse/fine verify level is lower than said threshold voltage level.
22. A method according to claim 16 , wherein: said first non-volatile storage element is a flash memory device.
23. A method for programming non-volatile storage, comprising: applying a first program voltage to a plurality of non-volatile storage elements; providing voltage conditions on bit lines for said non-volatile storage elements while applying said first program voltage; and making a first voltage change to bit lines for non-volatile storage elements in a fine programming mode while applying said first program voltage without making said first voltage change to bit lines for non-volatile storage elements in a coarse programming mode while applying said first program voltage.
24. A method according to claim 23 , wherein: said voltage conditions include an inhibit condition and a programming condition; and said first voltage change includes changing bit lines for non-volatile storage elements in said fine programming mode from said inhibit condition to said programming condition while applying said first program voltage.
25. A method according to claim 24 , wherein: said applying a first program voltage includes applying a voltage pulse; and said first voltage change is made during said voltage pulse.
26. A method according to claim 25 , wherein: said voltage pulse includes a first portion, a second portion and a third portion; said voltage pulse is at a lower magnitude during said second portion than in comparison to said first portion and said third portion; and said first voltage change is made during said second portion.
27. A method for programming non-volatile storage, comprising: applying one or more program pulses to a non-volatile storage element, said non-volatile storage element is in a coarse programming stage; maintaining a constant bit line voltage during said one or more pulses while said non-volatile storage element is in said coarse programming stage; verifying that said non-volatile storage element has reached a fine programming stage; applying one or more program pulses to said non-volatile storage element while said non-volatile storage element is in said fine programming stage; and changing said bit line voltage during said one or more pulses while said non-volatile storage element is in said fine programming stage.
28. A method according to claim 27 , wherein: said changing said bit line voltage during said one or more pulses includes changing between an inhibit voltage and a programming voltage.
29. A non-volatile storage system, comprising: a plurality of non-volatile storage elements; and a control circuit, said control circuit applies a first program voltage to said non-volatile storage elements and provides voltage conditions on bit lines for said non-volatile storage elements while applying said first program voltage, said control circuit makes a first voltage change to bit lines for non-volatile storage elements in said fine programming mode while applying said first program voltage without making said first voltage change to bit lines for non-volatile storage elements in said coarse programming mode while applying said first program voltage.
30. A non-volatile storage system according to claim 29 , wherein: said voltage conditions include an inhibit condition and a programming condition; and said first voltage change includes changing bit lines for non-volatile storage elements in said fine programming mode from said inhibit condition to said programming condition.
31. A non-volatile storage system according to claim 29 , wherein: said first program voltage includes a voltage pulse; and said first voltage change is made during said voltage pulse.
32. A non-volatile storage system according to claim 29 , wherein: said non-volatile storage elements are multi-state flash memory devices.
33. A non-volatile storage system according to claim 29 , wherein: said non-volatile storage elements are NAND flash memory devices.
34. A non-volatile storage system according to claim 29 , wherein said control circuit comprises: a plurality of sense circuits in communication with said non-volatile storage elements; coarse/fine storage devices in communication with said sense circuits; first selection circuits in communication with said coarse/fine storage devices and said non-volatile storage elements, said first selection circuits choose between two voltages to apply to said non-volatile storage elements based on said coarse/fine storage device; second selection circuits in communication with said coarse/fine storage devices, said second selection circuit choose between two verification parameters for said non-volatile storage elements.
35. A non-volatile storage system, comprising: a non-volatile storage element; a bit line and a word line in communication with said non-volatile storage element; a sense circuit in communication with said bit line; a coarse/fine storage device in communication with said sense circuit; a timer, said timer identifies a time during a program pulse applied to said non-volatile storage element using said word line; a first selection circuit in communication with said coarse/fine storage device and said timer and said bit line, said first selection circuit chooses between two voltages to apply to said bit line based on said timer identifying said time and said coarse/fine storage device; a second selection circuit in communication with said coarse/fine storage device and said sense circuit, said second selection circuit chooses between two verification parameters for said non-volatile storage element.
36. A non-volatile storage system according to claim 35 , wherein: said first selection circuit changes selection between said two voltages during said pulse.
37. A non-volatile storage system according to claim 35 , further comprising: said first selection circuit changes selection from an inhibit voltage to a programming voltage during said pulse.
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August 18, 2005
August 8, 2006
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