A method of nitriding a gate oxide layer by annealing a preformed oxide layer with nitric oxide (NO) gas in a hot wall, single wafer furnace is provided. The nitridation process can be carried out rapidly (i.e., at nitridation times of 30 seconds to 2 minutes) while providing acceptable levels of nitridation (i.e., up to 6 at. %) and desirable nitrogen/depth profiles. The nitrided gate oxide layer can optionally be reoxidized in a second oxidation step after the nitridation step. A gate electrode layer (e.g., boron doped polysilicon) can then be deposited on top of the nitrided gate oxide layer or on top of the reoxidized and nitrided gate oxide layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of nitriding a gate oxide layer on a semiconductor substrate comprising: nitriding the gate oxide layer in the presence of nitric oxide (NO) gas; wherein the nitriding step is conducted in a single wafer, hot wall furnace.
2. The method of claim 1 , wherein the gate oxide layer is nitrided at a temperature of from 900–1100° C.
3. The method of claim 2 , wherein the gate oxide layer is nitrided for 30 seconds to 2 minutes.
4. The method of claim 2 , further comprising depositing a gate electrode layer on top of the nitrided gate oxide layer on the substrate.
5. The method of claim 2 , wherein the gate oxide layer is nitrided for 2 minutes or less.
6. The method of claim 5 , wherein the nitrogen concentration in the gate oxide layer after nitriding is at least 2 at. %.
7. The method of claim 5 , wherein the nitrogen concentration in the gate oxide layer after nitriding is from about 4 at. % to about 6 at. %.
8. The method of claim 1 , further comprising oxidizing the nitrided gate oxide layer on the substrate.
9. The method of claim 1 , further comprising depositing a gate electrode layer on top of the nitrided gate oxide layer on the substrate.
10. The method of claim 9 , further comprising doping the gate electrode layer with a dopant.
11. The method of claim 10 , wherein the dopant is boron.
12. A semiconductor substrate made by the method of claim 1 .
13. The semiconductor substrate of claim 12 , wherein the semiconductor substrate is a CMOS device.
14. The semiconductor substrate of claim 12 , wherein the standard deviation of the oxide thickness on the substrate after nitriding is from about 0.1 to about 0.16 Å.
15. The semiconductor substrate of claim 14 , wherein the substrate has a nominal diameter of 8 inches.
16. A plurality of semiconductor substrates each made by the method of claim 1 , wherein the standard deviation of nitrogen content between the substrates is less than about 4 percent.
17. A semiconductor device comprising: a semiconductor substrate layer; a nitrided gate oxide layer disposed on the substrate layer to form a gate oxide/substrate interface; and a boron doped gate electrode layer disposed on the nitrided gate oxide layer; wherein the boron dopant in the gate electrode layer has been activated, and wherein the boron concentration in the semiconductor substrate layer at a distance of 5 nm or more from the gate oxide/substrate interface is no more than 1 percent of the average boron concentration in the gate electrode layer.
18. The semiconductor device of claim 17 , wherein the boron concentration in the substrate layer at a distance of 5 nm or more from the gate oxide/substrate interface is no more than 0.5 percent of the average boron concentration in the gate electrode layer.
19. The semiconductor device of claim 17 , wherein the boron dopant has been activated by annealing at a temperature of 950–1050° C.
20. The semiconductor device of claim 17 , wherein the average boron concentration in the gate electrode layer is at least 5×10 19 at/cm 3 .
21. The semiconductor device of claim 17 , wherein the substrate layer comprises silicon and wherein the gate electrode layer comprises polycrystalline silicon.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 13, 2002
August 22, 2006
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