A semiconductor memory device is operable in a full capacity mode and at least one reduced capacity mode, and includes a memory array having a plurality of memory blocks, each of the memory blocks having at least one word line. An address generation circuit generates a first multi-bit address signal having a logic value which is sequentially incremented by one during each of successive refresh periods. An address sorting circuit receives the first multi-bit address signal and outputs a second multi-bit address signal in which one or more least significant bits of the first multi-bit address signal are arranged in the second multi-bit address signal to indicate a memory block of the memory array, and in which remaining bits of the first multi-bit address signal are arranged in the second multi-bit address to indicate a word line within the selected memory block. The word lines of the memory array are refreshed according to the second multi-bit address signal.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory device operable in a full memory capacity mode and at least one reduced memory capacity mode, said memory device comprising: a memory array including a plurality of word lines; a refresh reference signal generator which generates a refresh reference signal pulse; and a row selection circuit, responsive to the refresh reference signal pulse, which non-sequentially selects the word lines during successive refresh operations in at least the full capacity mode.
2. The memory device of claim 1 , wherein the row selections circuit non-sequentially selects the word lines during successive refresh operations in at least one reduced capacity memory mode.
3. The memory device of claim 1 , wherein the row selection circuit comprises an address sorting circuit which rearranges parallel bits of a first row address signal which sequentially designates the word lines to obtain a second row address signal which non-sequentially designates the word lines.
4. The memory of claim 1 , wherein the memory device is a DRAM device.
5. The memory device of claim 1 , wherein the memory device is a UtRAM.
6. A semiconductor memory device comprising: a memory array having a plurality of memory blocks, each of memory blocks having at least one word line; and a refresh circuit which is operable in a full memory mode and a reduced memory mode, wherein the refresh circuit applies a refresh signal to the all of word lines during each of successive constant refresh cycle times in the full memory mode, and wherein the refresh circuit applies the refresh signal to a subset of the word lines during each of the successive constant refresh cycle times in the reduce memory mode; wherein, during each transition from the full memory mode to the reduced memory mode, all of the subset of the word lines receive the refresh signal within the constant refresh cycle time.
7. The semiconductor memory device of claim 6 , wherein, during each transition from the reduced memory mode to the full memory mode, all of the word lines receive the refresh signal within the constant refresh cycle time.
8. The semiconductor memory device of claim 7 , wherein the refresh circuit non-sequentially applies the refresh signal to the word lines in the full memory mode, and non-sequentially applies the refresh signal to the subset of word lines in the reduced memory mode.
9. The semiconductor memory of claim 6 , wherein the memory device is a DRAM device.
10. The semiconductor memory device of claim 6 , wherein the memory device is a UtRAM.
11. A semiconductor memory device which is operable in a full capacity mode and at least one reduced capacity mode, said device comprising: a memory array comprising a plurality of memory blocks, each of the memory blocks having at least one word line; an address generation circuit which generates a first multi-bit address signal having a logic value which is sequentially incremented by one during each of successive refresh periods; an address sorting circuit which receives the first multi-bit address signal and outputs a second multi-bit address signal in which one or more least significant bits of the first multi-bit address signal are arranged in the second multi-bit address signal to indicate a memory block of the memory array, and in which remaining bits of the first multi-bit address signal are arranged in the second multi-bit address to indicate a word line within the selected memory block; a row decoder which receives the second multi-bit address signal and which selects at least one word line according to the second multi-bit address during a refresh operation.
12. The semiconductor memory device of claim 11 , wherein the device is operable in N reduce memory capacity modes and the memory array comprises 2 N memory blocks, where N is an integer of 1 or more.
13. The semiconductor memory device of claim 12 , wherein the address sorting circuit arranges the N least significant bits of the first multi-bit address signal as the N most significant bits of the second multi-bit address signal.
14. The semiconductor memory device of claim 13 , wherein a total refresh cycle time during the full capacity memory mode and each reduced memory capacity mode is one times or a multiple of (N+1)*T, where T is the refresh period.
15. The semiconductor memory device of claim 14 , wherein the row decoder selects at least one word line according to the second multi-bit address during each successive refresh period T in the full capacity mode, and wherein the row decoder selects at least one word line according to the second multi-bit address signal during each successive multiple of the refresh period T during the reduced capacity memory mode.
16. The semiconductor memory device of claim 15 , wherein the at least one reduced capacity memory mode includes a one-half capacity memory mode, and wherein the row decoder selects at least one word line according to the second multi-bit address signal during each successive refresh period 2*T during the one-half capacity memory mode.
17. The semiconductor memory device of claim 16 , wherein the at least one reduced capacity memory mode includes a one-quarter capacity memory mode, and wherein the row decoder selects at least one word line according to the second multi-bit address signal during each successive refresh period 4*T during the one-quarter capacity memory mode.
18. The semiconductor memory device of claim 17 , wherein the at least one reduced capacity memory mode includes a one-eighth capacity memory mode, and wherein the row decoder selects at least one word line according to the second multi-bit address signal during each successive refresh period 8*T during the one-eighth capacity memory mode.
19. The semiconductor memory device of claim 16 , wherein N=1, wherein the first multi-bit address signal has bits A 0 . . . An, and the second multi-bit address signal has bits R 0 . . . Rn, where n is an integer of 1 or more, and wherein the address sorting circuit arranges the bit A 0 of the first multi-bit address signal as the bit Rn of the second multi-bit address signal, and the bits A 1 . . . An of the first multi-bit address signal as the respective bits R 0 . . . Rn- 1 of the second multi-bit address signal.
20. The semiconductor memory device of claim 17 , wherein N=2, wherein the first multi-bit address signal has bits A 0 . . . An, and the second multi-bit address signal has bits R 0 . . . Rn, where n is an integer of 2 or more, and wherein the address sorting circuit arranges the bits A 0 and A 1 of the first multi-bit address signal as the respective bits Rn and Rn-l of the second multi-bit address signal, and the bits A 2 . . . An of the first multi-bit address signal as the respective bits R 0 . . . Rn- 2 of the second multi-bit address signal.
21. The semiconductor memory device of claim 18 , wherein N=3, wherein the first multi-bit address signal has bits A 0 . . . An, and the second multi-bit address signal has bits R 0 . . . Rn, where n is an integer of 3 or more, and wherein the address sorting circuit arranges the bits A 0 , A 1 and A 2 of the first multi-bit address signal as the respective bits Rn, Rn- 1 and Rn- 2 of the second multi-bit address signal, and the bits A 3 . . . An of the first multi-bit address signal as the respective bits R 0 . . . Rn- 3 of the second multi-bit address signal.
22. The semiconductor memory of claim 11 , wherein the memory device is a DRAM device.
23. The semiconductor memory device of claim 11 , wherein the memory device is a UtRAM.
24. A memory device operable in a full memory capacity mode and N reduced memory capacity modes, where N is an integer of 1 or more, said memory device comprising: a memory array comprising m memory blocks each having at least one word line, where m is an integer 2 N or more; a refresh reference signal generator which generates a refresh reference signal pulse having a period T; an refresh address generation circuit which generates a first n-bit address signal having bits A 0 , A 1 , . . . , An, wherein n is an integer greater than or equal to N, and wherein a logic value of the n-bit address signal is sequentially incremented by 1 at each period T of the refresh reference pulse signal; a refresh controller which generates a refresh main signal according to a mode control signal and bits A 0 . . . A(N−1) of the first address signal; an address converter which generates a second n-bit address signal having bits R 0 , R 1 , . . . , Rn, wherein the second parallel n-bit address signal is generated at a timing of the refresh main signal, wherein the bits A 0 . . . A(N−1) of the first parallel n-bit address signal are respectively output as the bits Rn . . . R(n−(N−1))of the second n-bit address signal, and wherein the bits A(N) . . . An of the first n-bit address signal are respectively output as the bits R 0 . . . R(n−(N−2)) of the second n-bit parallel signal; and a row decoder which addresses a word line of the memory array according to the second n-bit parallel signal at a timing of the refresh main signal.
25. The memory device of claim 24 , wherein a total refresh cycle time during the full capacity memory mode and each reduced memory capacity mode is one times or a multiple of (N+1)*T.
26. The memory device of claim 24 , wherein the at least one reduced capacity memory mode includes a one-half capacity memory mode, wherein the refresh main signal has a period 2*T during the one-half capacity memory mode, and wherein the row decoder selects at least one word line according to the second multi-bit address signal during each successive period 2*T during the one-half capacity memory mode.
27. The memory device of claim 24 , wherein the at least one reduced capacity memory mode includes a one-quarter capacity memory mode, wherein the refresh main signal has a period 4*T during the one-quarter capacity memory mode, and wherein the row decoder selects at least one word line according to the second multi-bit address signal during each successive period 4*T during the one-quarter capacity memory mode.
28. The memory device of claim 24 , wherein the at least one reduced capacity memory mode includes a one-eighth capacity memory mode, wherein the refresh main signal has a period 8*T during the one-eighth capacity memory mode, and wherein the row decoder selects at least one word line according to the second multi-bit address signal during each successive period 8*T during the one-eighth capacity memory mode.
29. The memory device of claim 26 , wherein N=1 such that address converter arranges the bit A 0 of the first multi-bit address signal as the bit Rn of the second multi-bit address signal, and the bits A 1 . . . An of the first multi-bit address signal as the respective bits R 0 . . . Rn- 1 of the second multi-bit address signal.
30. The memory device of claim 27 , wherein N=2 such that the address sorting circuit arranges the bits A 0 and A 1 of the first multi-bit address signal as the respective bits Rn and Rn- 1 of the second multi-bit address signal, and the bits A 2 . . . An of the first multi-bit address signal as the respective bits R 0 . . . Rn- 2 of the second multi-bit address signal.
31. The memory device of claim 28 , wherein N=3 such the address converter arranges the bits A 0 , A 1 and A 2 of the first multi-bit address signal as the respective bits Rn, Rn- 1 and Rn- 2 of the second multi-bit address signal, and the bits A 3 . . . An of the first multi-bit address signal as the respective bits R 0 . . . Rn- 3 of the second multi-bit address signal.
32. The memory of claim 24 , wherein the memory device is a DRAM device.
33. The memory device of claim 24 , wherein the memory device is a UtRAM.
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August 30, 2004
August 22, 2006
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