Dynamic semiconductor memory device

1. A dynamic semiconductor memory device comprising: memory cell groups oppositely disposed on one side and the other side; multiple bit line pairs, on one side, connected to said memory cell group on the one side; multiple bit line pairs, on the other side, connected to said memory cell group on the same other side and; a shared sense amplifier, which is provided in between said memory cell groups on one side and the other side, and controls said bit line pair on the one side and said bit line pair on the other side; said shared sense amplifier comprising; an equalizer circuit, on one side, connected to each of said bit line pair on the one side; an equalizer circuit, on the other side, connected to each of said bit line pair on the same other side; one or a multiple of said equalizer circuits on one side, and one or a multiple of said equalizer circuits on the other side; and one current-limiting element that supplies a bit line precharge potential to one or a multiple of said equalizer circuits on one side and the other side; wherein said memory cell group on one side and said memory cell group on the other side are assigned to different units in terms of a unit of memory cell group, connected to each of said equalizer circuit on one side and said equalizer circuit on the other side, sharing said one current-limiting element, that is to be replaced by the same group in column redundancy, termed “column replacement segment” hereafter.

2. A dynamic semiconductor memory device comprising; memory cell groups oppositely disposed on one side and the other side; multiple bit line pairs, on one side, connected to said memory cell group on the one side; multiple bit line pairs, on the other side, connected to said memory cell group on the other side; and a shared sense amplifier, which is provided in between said memory cell groups on one side and the other side, and controls said bit line pair on the one side and said bit line pair on the other side; said shared sense amplifier comprising; an equalizer circuit, on one side, connected to each of said bit line pair on the one side; and an equalizer circuit, on the other side, connected to each of said bit line pair on the other side; wherein a first column selecting line is set to an active state and one or a multiple of said bit line pair, which is on one side and performs write/read operation, is replaced by a column redundancy bit line pair as a set when said memory cell group on one side is in an active state; said first column selecting line is set to an active state and one or a multiple of said bit line pair, which is on the other side and performs write/read operation, is replaced by a column redundancy bit line pair as a set when said memory cell group on the other side is in an active state; one current-limiting element, which commonly supplies a bit line precharge potential to said equalizer circuit, on one side, connected to each of one or a multiple of said bit line pair on the same side, and to said equalizer circuit, on the other side, connected to each of one or a multiple of said bit line pair on the same side is provided; and said memory cell group on one side and said memory cell group on the other side are assigned to different units in terms of a unit of memory cell group, connected to each of said equalizer circuit on one side and said equalizer circuit on the other side, sharing said current-limiting element, that is to be replaced by the same group in column redundancy termed “column replacement segment” hereafter.

3. The dynamic semiconductor memory device as defined in claim 1 wherein said current-limiting element comprises a PMOS transistor whose first terminal is connected to a bit line precharge power supply and second terminal is connected in common to said equalizer circuits on one side and the other side as a power supply terminal supplying said bit line precharge potential.

4. The dynamic semiconductor memory device as defined in claim 2 wherein said current-limiting element comprises a PMOS transistor whose first terminal is connected to a bit line precharge power supply and second terminal is connected in common to said equalizer circuits on one side and the other side as a power supply terminal supplying said bit line precharge potential.

5. The dynamic semiconductor memory device as defined in claim 3 wherein at least one of a reference voltage (GND), the substrate voltage of a memory cell transistor (VBB), and the standby voltage of a word line (VKK) is supplied to the gate of said PMOS transistor.

6. The dynamic semiconductor memory device as defined in claim 4 wherein at least one of a reference voltage (GND), the substrate voltage of a memory cell transistor (VBB), and the standby voltage of a word line (VKK) is supplied to the gate of said PMOS transistor.

7. The dynamic semiconductor memory device as defined in claim 3 wherein said PMOS transistor is provided in the same N-well region as an N-well, where a PMOS transistor, which constitutes a PMOS sense circuit constituting said shared sense amplifier, is disposed.

8. The dynamic semiconductor memory device as defined in claim 4 wherein said PMOS transistor is provided in the same N-well region as an N-well, where a PMOS transistor, which constitutes a PMOS sense circuit constituting said shared sense amplifier, is disposed.

9. The dynamic semiconductor memory device in claim 1 wherein a capacitor plate layer, which is connected commonly to one ends of multiple cell capacitors of a memory cell group, is used as the wiring layer of the wiring that supplies a bit line precharge potential commonly to one or a multiple of said equalizer circuits on one side and one or a multiple of said equalizer circuits on the other side from said current-limiting element.

10. The dynamic semiconductor memory device in claim 2 wherein a capacitor plate layer, which is connected commonly to one ends of multiple cell capacitors of a memory cell group, is used as the wiring layer of the wiring that supplies a bit line precharge potential commonly to one or a multiple of said equalizer circuits on one side and one or a multiple of said equalizer circuits on the other side from said current-limiting element.

11. The dynamic semiconductor memory device in claim 1 comprising means for variably switch-controlling the limit current level of said current-limiting element.

12. The dynamic semiconductor memory device in claim 2 comprising means for variably switch-controlling the limit current level of said current-limiting element.

13. The dynamic semiconductor memory device in claim 3 comprising means for switching to a voltage selected from a reference voltage, the substrate voltage of a memory cell transistor, and the standby voltage of a word line as the voltage supplied to the gate of a PMOS transistor constituting said current-limiting element.

14. The dynamic semiconductor memory device in claim 4 comprising means for switching to a voltage selected from a reference voltage, the substrate voltage of a memory cell transistor, and the standby voltage of a word line as the voltage supplied to the gate of a PMOS transistor constituting said current-limiting element.

15. The dynamic semiconductor memory device as defined in claim 11 wherein the limit current level of said current-limiting element is switched based on the test mode.

16. The dynamic semiconductor memory device as defined in claim 12 wherein the limit current level of said current-limiting element is switched based on the test mode.

17. The dynamic semiconductor memory device as defined in claim 9 wherein a fuse that variably controls the limit current level of said current-limiting element based on whether it is cut or not is provided, and the limit current level of said current-limiting element is switched by cutting a fuse.

18. The dynamic semiconductor memory device as defined in claim 10 wherein a fuse that variably controls the limit current level of said current-limiting element based on whether it is cut or not is provided, and the limit current level of said current-limiting element is switched by cutting a fuse.

19. A dynamic semiconductor memory device comprising: two memory arrays, each having redundant cells, oppositely disposed on one side and the other side and; a sense amplifier circuit connected in between said two memory arrays and wherein; said sense amplifier circuit comprises; an equalizer circuit on one side having two active elements, provided for a bit line pair of said memory array on one side, one end of which is connected to each of said bit line pair, and driving each of said bit line pair to a bit precharge voltage during a precharge equalizing operation according to a bit precharge voltage inputted into the other end, and one active element inserted in between said bit line pair, and wherein the control terminals of said three active elements are connected in common to a first equalizer control signal; an equalizer circuit on the other side having two active elements, provided for a bit line pair of said memory array on the other side, one end of which is connected to each of said bit line pair, and driving each of said bit line pair to a bit precharge voltage during a precharge equalizing operation according to a bit precharge voltage inputted into the other end, and one active element inserted in between said bit line pair, and wherein the control terminals of said three active elements are connected in common to a second equalizer control signal; a sense circuit receiving a voltage of a bit line pair at a first and second nodes, differentially amplifying and outputting it to said first and second nodes; a first switch performing on/off control of a connection between ends of a bit line pair connected to said equalizer circuit on one side and the first and second nodes of said sense circuit based on an inputted control signal; a second switch performing on/off control of a connection between ends of a bit line pair connected to said equalizer circuit on the other side and the first and second nodes of said sense circuit based on an inputted control signal and; a switch performing on/off control of an IO line that corresponds to the fist and second nodes of said sense circuit based on an inputted column selecting signal, and; a current-limiting element, provided commonly for a pair of said equalizer circuit on one side and the other side, whose one end is connected to a bit line precharge power supply, into whose control terminal a prescribed voltage is inputted, whose other end is commonly connected to said other end of two active elements driving said bit line pair to a bit precharge voltage, is provided, wherein said memory cell group on one side and said memory cell group on the other side are assigned to different units in terms of a unit of memory cell group, connected to each of said equalizer circuit on one side and said equalizer circuit on the other side, sharing said one current-limiting element, that is to be replaced by the same group in column redundancy termed “column replacement segment” hereafter.

20. The dynamic semiconductor memory device as defined in claim 19 wherein; said current-limiting element is provided commonly for said multiple equalizer circuits on one side and multiple said equalizer circuits on the other side and; one end of said current-limiting element is connected to a bit line precharge power supply, a prescribed voltage is inputted into a control terminal, the other end is commonly connected to said other end of two active elements driving said bit line pair to a bit precharge potential in said multiple equalizer circuits on one side, and is commonly connected to said other end of two active elements driving said bit line pair to a bit precharge voltage in said multiple equalizer circuits on the other side.

21. The dynamic semiconductor memory device as defined in claim 20 wherein the data of a bit line pair connected to said multiple equalizer circuits on one side and a bit line pair connected to said multiple equalizer circuits on the other side is connected to an IO line that corresponds through a switch turned on/off by a common column selecting signal.