A gain cell for a memory circuit, a memory circuit formed from multiple gain cells, and methods of fabricating such gain cells and memory circuits. The memory gain cell includes a storage capacitor, a write device electrically coupled with the storage capacitor for charging and discharging the storage capacitor to define a stored electrical charge, and a read device. The read device includes one or more semiconducting carbon nanotubes each electrically coupled between a source and drain. A portion of each semiconducting carbon nanotube is gated by the read gate and the storage capacitor to thereby regulate a current flowing through each semiconducting carbon nanotube from the source to the drain. The current is proportional to the electrical charge stored by the storage capacitor. In certain embodiments, the memory gain cell may include multiple storage capacitors.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory gain cell comprising: a first storage capacitor capable of holding a stored electrical charge; and a read device including a source, a drain, a read gate, and at least one semiconducting carbon nanotube with a first end electrically coupled with said source, a second end electrically coupled with said drain, and a first portion located between said first and second ends, said first portion being gated by said read gate and said first storage capacitor to thereby regulate a current flowing through said at least one semiconducting carbon nanotube from said source to said drain, said current flowing through said at least one semiconducting carbon nanotube, when said first portion is gated, being dependent upon said electrical charge stored by said first storage capacitor.
2. The memory gain cell of claim 1 further comprising: a write device electrically coupled with said first storage capacitor and adapted to charge and discharge said first storage capacitor to define said stored electrical charge.
3. The memory gain cell of claim 2 wherein said write device comprises a MOSFET.
4. The memory gain cell of claim 1 wherein said first portion is positioned between said first storage capacitor and said read gate.
5. The memory gain cell of claim 1 wherein said at least one semiconducting carbon nanotube includes a second portion that overlies said first storage capacitor.
6. The memory gain cell of claim 1 further comprising: a second storage capacitor capable of holding a stored electrical charge, said electrical charge stored by said second storage capacitor affecting said current being flowing through said at least one semiconducting carbon nanotube when said first portion is gated by said read device.
7. The memory gain cell of claim 6 wherein said at least one semiconducting carbon nanotube includes a second portion overlying said second storage capacitor and said first portion does not overlie said second storage capacitor.
8. The memory gain cell of claim 6 further comprising: a write device electrically coupled with said second storage capacitor and adapted to charge and discharge said second storage capacitor to define said stored electrical charge.
9. The memory gain cell of claim 8 wherein said write device comprises a MOSFET.
10. The memory gain cell of claim 1 further comprising: a shunt of a conductive material adapted to gate said at least one semiconducting carbon nanotube between said first and second ends over at least one second portion not coinciding with said first portion.
11. The memory gain cell of claim 10 wherein said shunt is isolated electrically from said at least one second portion so that said at least one second portion is gated by said shunt only when said first portion is gated by said read gate.
12. The memory gain cell of claim 10 wherein said shunt is electrically coupled with said at least one second portion so that said at least one second portion is continuously gated.
13. A memory circuit comprising an interconnected plurality of memory gain cells of claim 1 arranged in a memory cell array.
14. A memory gain cell comprising: a storage capacitor; a write device electrically coupled with said storage capacitor and adapted to charge and discharge said storage capacitor to define a stored electrical charge; and a read device including a source, a drain, a read gate overlying said storage capacitor, and at least one semiconducting carbon nanotube with a first end electrically coupled with said source, a second end electrically coupled with said drain, and a portion between said first end and said second end, said portion being disposed between said storage capacitor and said read gate such that said portion is gated by said read gate and said storage capacitor to thereby regulate a current flowing through said at least one semiconducting carbon nanotube from said source to said drain, said current being dependent upon said stored electrical charge of said storage capacitor.
15. The memory gain cell of claim 14 wherein said read gate changes a resistivity of said portion of said at least one semiconducting carbon nanotube when voltage is supplied to said read gate effective to gate said portion.
16. The memory gain cell of claim 14 wherein said stored electrical charge stored by said storage capacitor changes a resistivity of said portion of said at least one semiconducting carbon nanotube.
17. The memory gain cell of claim 14 wherein said write device comprises a MOSFET.
18. The memory gain cell of claim 17 wherein said MOSFET comprises: a drain electrically coupled with said storage capacitor; a source; a channel region flanked by said source and said drain of said MOSFET; and a gate electrode electrically isolated from said channel region, said gate electrode operative for controlling a resistivity of said channel region for charging and discharging said stored charge of said storage capacitor by transferring carriers from said source of said MOSFET to said drain of said MOSFET.
19. A memory circuit comprising an interconnected plurality of memory gain cells of claim 14 arranged in a memory cell array.
20. A memory gain cell comprising: first and second storage capacitors; first and second write devices each electrically coupled with one of said first and second storage capacitors and each adapted to individually charge and discharge a corresponding one of said first and second storage capacitors to define a corresponding stored electrical charge; and a read device including a source, a drain, a read gate, and at least one semiconducting carbon nanotube with a first end electrically coupled with said source, a second end electrically coupled with said drain, and a first portion between said first end and said second end, said first portion being gated by said read gate and said first and second storage capacitors to thereby regulate a current flowing through said at least one semiconducting carbon nanotube from said source to said drain, said current being dependent upon said stored electrical charge held by each of said first and second storage capacitors.
21. The memory gain cell of claim 20 wherein said at least one semiconducting carbon nanotube includes a second portion between said first end and said first portion and a third portion between said second end and said first portion, said second portion overlying said first storage capacitor and said third portion overlying said second storage capacitor.
22. The memory gain cell of claim 21 wherein said read gate changes a resistivity of said first portion of said at least one semiconducting carbon nanotube when voltage is supplied to said read gate effective to gate said first portion.
23. The memory gain cell of claim 21 wherein said stored electrical charge of said first storage capacitor changes a resistivity of said second portion of said at least one semiconducting carbon nanotube.
24. The memory gain cell of claim 21 wherein said stored electrical charge of said second storage capacitor changes a resistivity of said third portion of said at least one semiconducting carbon nanotube.
25. The memory gain cell of claim 20 wherein said first and second storage capacitors are separated by an isolation region, and said first portion of said at least one semiconducting carbon nanotube is disposed between said isolation region and said read gate.
26. The memory gain cell of claim 20 wherein said current flowing through said at least one semiconducting carbon nanotube when gated by said read device is contingent upon said stored electrical charge of each of said first and second storage capacitors.
27. The memory gain cell of claim 20 wherein each of said first and second write devices comprises a MOSFET.
28. The memory gain cell of claim 27 wherein said MOSFET comprises: a drain electrically coupled with said storage capacitor; a source; a channel region flanked by said source and said drain of said MOSFET; and a gate electrode electrically isolated from said channel region, said gate electrode operative for controlling a resistivity of said channel region for charging and discharging said stored charge of a corresponding one of said first and second storage capacitors by transferring carriers from said source of said MOSFET to said drain of said MOSFET.
29. A memory circuit comprising an interconnected plurality of memory gain cells of claim 20 arranged in a memory cell array.
30. A memory gain cell comprising: first and second storage capacitors; first and second write devices each electrically coupled with one of said first and second storage capacitors and each adapted to individually charge and discharge a corresponding one of said first and second storage capacitors to define a corresponding stored electrical charge; a read device including a source, a drain, first and second read gates, and at least one semiconducting carbon nanotube with a first end electrically coupled with said source, a second end electrically coupled with said drain, and first and second portions between said first end and said second end, said first portion being gated by said first read gate and said first storage capacitor and said second portion being gated by said second read gate and said second storage capacitor to thereby regulate a current flowing through said at least one semiconducting carbon nanotube from said source to said drain, said current being dependent upon said stored electrical charge held by each of said first and second storage capacitors; and a shunt of a conductive material adapted to gate said at least one semiconducting carbon nanotube between said first and second ends over at least one third portion not coinciding with said first and second portions.
31. The memory gain cell of claim 30 wherein said shunt is configured to gate said at least one third portion by changing a resistivity of said at least one third portion only when said first and second portions are gated by said first and second read gates.
32. The memory gain cell of claim 30 wherein said shunt is configured to continuously gate said at least one third portion by changing a resistivity of said at least one third portion.
33. The memory gain cell of claim 30 wherein said first read gate changes a resistivity of said first portion of said at least one semiconducting carbon nanotube when voltage is supplied to said first read gate effective to gate said first portion.
34. The memory gain cell of claim 30 wherein said second read gate changes a resistivity of said second portion of said at least one semiconducting carbon nanotube when voltage is supplied to said second read gate effective to gate said second portion.
35. The memory gain cell of claim 30 wherein said stored electrical charge of said first storage capacitor changes a resistivity of said first portion of said at least one semiconducting carbon nanotube.
36. The memory gain cell of claim 30 wherein said stored electrical charge of said second storage capacitor changes a resistivity of said second portion of said at least one semiconducting carbon nanotube.
37. The memory gain cell of claim 30 wherein said current flowing through said at least one semiconducting carbon nanotube when gated by said first and second read gates is contingent upon said stored electrical charge of each of said first and second storage capacitors.
38. The memory gain cell of claim 30 wherein each of said first and second write devices comprises a MOSFET.
39. The memory gain cell of claim 38 wherein said MOSFET comprises: a drain electrically coupled with said storage capacitor; a source; a channel region flanked by said source and said drain of said MOSFET; and a gate electrode electrically isolated from said channel region, said gate electrode operative for controlling a resistivity of said channel region for charging and discharging said stored charge of a corresponding one of said first and second storage capacitors by transferring carriers from said source of said MOSFET to said drain of said MOSFET.
40. The memory gain cell of claim 30 wherein said first read device is vertically stacked over said first storage capacitor.
41. The memory gain cell of claim 30 wherein said second read device is vertically stacked over said second storage capacitor.
42. A memory circuit comprising an interconnected plurality of memory gain cells of claim 30 arranged in a memory cell array.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 29, 2004
September 19, 2006
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