A data reproducing controller for operating a device for reproducing data at a high speed, which is recorded on a disc and includes an error correction code. A PI correction circuit performs an error correction process on a PI and causes a completion signal to go high whenever processing of 182 bytes of data is completed. A counter circuit sequentially increments a count value whenever the completion signal goes high. A determination circuit compares the count value with a predetermined set value and determines whether the data of which PI has undergone the error correction process is a PO row based on the comparison. The determination circuit causes a first control signal to go low when the data is a PO row. A descrambling circuit skips the data that is determined to be a PO row.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A data reproducing controller for controlling reproduction of recording data, wherein the recording data is in sectors with each sector including a predetermined number of rows of scrambled data with each row having a predetermined number of bytes, a first error correction code added to each row of the scrambled data, a second correction code added to the predetermined number of rows of scrambled data, the data reproducing controller comprising: a first error correction circuit for performing a first error correction process on the scrambled data in units of rows in accordance with the first error correction code; a descrambling circuit for performing a descrambling process on the scrambled data that has undergone the first error correction process to generate descrambled data; a counter for counting the scrambled data in units of rows; and a determination circuit for detecting a timing at which the second error correction code is provided to the descrambling circuit from the count value and for inactivating the descrambling process when the second error correction code is provided to the descrambling circuit.
2. The data reproducing controller according to claim 1 , further comprising: an access circuit for storing the descrambled data in a buffer memory.
3. A data reproducing controller for controlling reproduction of recording data, wherein the recording data is in sectors with each sector including a predetermined number of rows of scrambled data with each row having a predetermined number of bytes, a first error correction code added to each row of the scrambled data, a second correction code added to the predetermined number of rows of scrambled data, the data reproducing controller comprising: a first error correction circuit for performing a first error correction process on the scrambled data in units of rows in accordance with the first error correction code; a descrambling circuit for performing a descrambling process on the scrambled data that has undergone the first error correction process to generate descrambled data; a counter for counting the scrambled data in units of rows; and a determination circuit for detecting a timing at which the second error correction code is provided to the descrambling circuit from the count value and for inactivating the descrambling process when the second error correction code is provided to the descrambling circuit; an access circuit for storing the descrambled data in a buffer memory; a scrambling circuit for retrieving and performing a scrambling process on the descrambled data stored in the buffer memory; and a second error correction circuit for performing a second error correction process on the scrambled data in accordance with the second error correction code.
4. The data reproducing controller according to claim 1 , wherein each sector of the recording data includes an error detection code, the controller further comprising: an error detection circuit for performing an error detection process in accordance with the error detection code on the scrambled data that has undergone the first error correction process by the first correction circuit, wherein the error detection circuit skips the error detection process of the second error correction code in response to an instruction provided from the determination circuit.
5. The data reproducing controller according to claim 4 , further comprising: an access circuit for storing the descrambled data in a buffer memory.
6. The data reproducing controller according to claim 5 , further comprising: a scrambling circuit for retrieving and performing a scrambling process on the descrambled data stored in the buffer memory; and a second error correction circuit for performing a second error correction process on the scrambled data in accordance with the second error correction code.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 8, 2005
September 26, 2006
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