A system and method for enabling multithreading in a embedded processor, invoking zero-time context switching in a multithreading environment, scheduling multiple threads to permit numerous hard-real time and non-real time priority levels, fetching data and instructions from multiple memory blocks in a multithreading environment, and enabling a particular thread to modify the multiple states of the multiple threads in the processor core.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A multithreaded computer based system for enabling a command in a first thread to access data in a second thread comprising: an embedded pipelined processor capable of having a first program thread and a second program thread in an execution pipeline, said first program thread comprising a first set of instructions, said second program thread comprising a second set of instructions, said embedded processor comprising: a fetch unit for fetching an instruction from program memory; a decode unit for decoding said fetched instruction; an execution unit for executing said decoded instruction; and a write back unit for writing the results of said executed instruction to an identified storage location; a first set of data storage devices capable of storing a first state of said embedded processor, wherein said first state is the state of the embedded processor during the execution of the first program thread; a second set of data storage devices capable of storing a second state of said embedded processor, wherein said second state is the state of the embedded processor during the execution of the second program thread; wherein at least said first set of data storage devices includes a first control status register for identifying a first target set of data storage devices from which a first source operand of a fetched instruction is to be retrieved and for identifying a second target set of data storage devices to which a first result of an executed instruction is to be stored, wherein at least one of said first or said second target set of data storage devices is not included in the first set of data storage devices; a thread scheduler for identifying which of said program threads said embedded processor executes; and an instruction set including an instruction that overwrites the first control status register when instructions associated with the first set of data storage devices are executed and overwrites a second control status register when instructions associated with the second set of data storage devices are executed; wherein said processor switches between said first and second state in a time period between the end of the execution of a first program instruction in the first thread and the beginning of the execution of a second program instruction in the second thread; wherein said processor switches between said first and second states by changing a state selection register.
2. The multithreaded computer based system of claim 1 , wherein the embedded pipelined processor further includes a peripheral block.
3. The multithreaded computer based system of claim 2 , wherein the peripheral block is one of a phase locked loop and a watchdog timer.
4. The multithreaded computer based system of claim 1 , wherein the embedded pipelined processor further includes an internal memory unit comprising a flash memory with a shadow static memory.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 22, 2001
October 10, 2006
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