Integrated semiconductor circuit with an electrically programmable switching element

1. An integrated semiconductor circuit having an electrically programmable switching element, which can be switched once from an electrically insulating state into an electrically conductive state by applying a programming voltage, where the switching element has a substrate electrode, produced in a substrate, which can be electrically biased with a substrate potential, and an opposing electrode, which is isolated from the substrate electrode by an insulating layer, where the substrate electrode comprises at least one highly doped substrate region, and where the opposing electrode can be connected to an external first electrical potential, which can be provided outside of the semiconductor circuit, wherein the substrate electrode can be connected, for the purpose of programming the switching element, to a second electrical potential, which is provided by the semiconductor circuit, and which, together with the external first potential, provides a higher programming voltage than the external first potential together with the substrate potential, wherein said insulating layer is damaged by said higher programming voltage such that an electrical connection exists between said substrate electrode and said opposing electrode after said programming, and wherein the substrate electrode is shielded from the substrate potential by a current barrier layer, which when the switching element is programmed, prevents a flow of current between the substrate electrode and a region of the substrate, which has been biased with the substrate potential.

2. The semiconductor circuit as claimed in claim 1 , wherein the current barrier layer is a doped intermediate layer which has the opposite doping from that of the substrate, which surrounds the intermediate layer.

3. The semiconductor circuit as claimed in claim 2 , wherein the substrate electrode comprises a weakly doped substrate region, which surrounds the highly doped substrate region, and which has the opposite doping from that of the current barrier layer.

4. The semiconductor circuit as claimed in claim 1 , wherein the current barrier layer can be connected to a blocking potential for the purpose of programming the switching element, which results in reverse biased pn-junctions between the current barrier layer and the substrate and between the current barrier layer and the substrate electrode.

5. The semiconductor circuit as claimed in claim 1 , wherein the highly doped substrate region of the substrate electrode and the current barrier layer are n-doped, wherein a region of the substrate, which can be biased with the substrate potential and the weakly doped substrate region are p-doped, and wherein the blocking potential is higher than the substrate potential.

6. The semiconductor circuit as claimed in claim 1 , wherein the current barrier layer is an electrical insulating layer.

7. The semiconductor circuit as claimed in claim 1 , wherein the current barrier layer comprises a buried layer beneath the wealdy doped substrate region and comprises side insulations, which surround the switching element at the sides and extend as far as the buried layer.

8. The semiconductor circuit as claimed in claim 1 , wherein the opposing electrode is a gate electrode, which is isolated from the substrate electrode by a gate oxide layer.

9. The semiconductor circuit as claimed in claim 8 , wherein the highly doped substrate region of the substrate electrode comprises two source/drain implantations, which are shorted to one another.

10. The semiconductor circuit as claimed in claim 9 , wherein a channel doping of the same doping type as the doping type of the source/drain implantations is introduced into the substrate between the two source/drain implantations.

11. The semiconductor circuit as claimed in claim 1 , wherein the semiconductor circuit has a plurality of switching elements, which are shielded from a substrate region which can be biased with the substrate potential by a common current barrier layer, and whose substrate electrodes are shorted to one another, and whose opposing electrodes are shorted to one another.

12. The semiconductor circuit as claimed in claim 1 , wherein the semiconductor circuit is a memory circuit, preferably a memory circuit in a dynamic read/write memory.

13. The semiconductor circuit as claimed in claim 1 , wherein the programmable switch element comprises an antifuse.

14. A circuit having an electrically programmable element for switching from an electrically insulating state to an electrically conductive state comprising: a semiconductor substrate having a first doping, said substrate connected to a substrate potential; a well defined in said substrate, said well having a second doping; a current barrier layer, having a third doping, formed between said substrate and said well; a substrate electrode defined in said well; a first terminal connected to said well and said substrate electrode; a well potential or voltage for selectively connecting to said first terminal, said well potential less than said substrate potential; an opposing electrode connected to a second terminal; a programming potential for connecting to said second terminal, said programming potential greater than said substrate potential; and an insulating layer between said substrate electrode and said opposing electrode, said insulating layer made of a material that is damaged when said well voltage is connected to said first terminal at the same time said programming voltage is connected to said second terminal such that said damaged insulating layer provides an electrical connection between said substrate electrode and said opposing electrode.

15. The circuit of claim 14 , wherein the current barrier layer is a doped intermediate layer which has the opposite doping from that of the substrate, which surrounds the intermediate layer.

16. The circuit of claim 14 , wherein the substrate electrode comprises a weakly doped substrate region, which surrounds the highly doped substrate region, and which has the opposite doping from that of the current barrier layer.

17. The circuit of claim 14 , wherein the current barrier layer is connected to a blocking potential during the programming of said element, said blocking potential creating a reverse biased pn-junction between the current barrier layer and the substrate and between the current barrier layer and the substrate electrode.

18. The circuit of claim 14 , wherein the substrate electrode is highly doped and comprises two source/drain implantations, which are shorted to each other.

19. The circuit of claim 14 , wherein said circuit is a memory circuit in a dynamic read/write memory.

20. The circuit of claim 17 , wherein the substrate electrode and the current barrier layer are n-doped, the substrate and the well region are p-doped and wherein the blocking potential is higher than the substrate potential.