A semiconductor electronic device is described comprising a die of semiconductor material having a plurality of contact pads electrically connected to a support for example through interposition of contact wires, said plurality of contact pads comprising signal pads and power pads, the device being characterized in that said signal pads are implemented on the die of semiconductor material with a mutual pitch lower than the pitch between said power pads.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor electronic device comprising a die of semiconductor material having a plurality of contact pads electrically connected to a support, said plurality of contact pads comprising signal pads and power pads, wherein said signal pads are implemented on the die of semiconductor material with a pitch narrower than a pitch between said power pads, wherein the pitch between the signal pads is less than 90 microns and the pitch between the power pads is equal or more than 90 microns.
2. The semiconductor electronic device according to claim 1 wherein said signal pads and said power pads are implemented in distinct regions of the die of semiconductor material.
3. A semiconductor electronic device comprising a die of semiconductor material having a plurality of contact pads electrically connected to a support, said plurality of contact pads comprising signal pads and power pads, wherein said signal pads are implemented on the die of semiconductor material with a pitch narrower than a pitch between said power pad, wherein said signal pads have a multilayer structure comprising metallic layers alternated by insulating material layers and upperly ending with a terminal metallic material layer.
4. The semiconductor electronic device according to claim 3 wherein said upper terminal metallic material layer of said signal pads has a thickness less than or equal to 2 microns.
5. A semiconductor electronic device comprising a die of semiconductor material having a plurality of contact pads electrically connected to a support, said plurality of contact pads comprising signal pads and power pads, wherein said signal pads are implemented on the die of semiconductor material with a pitch narrower than a pitch between said power pad, wherein said power pads have a multilayer structure comprising first metallic layers alternated by insulating material layers and upperly ending with a second terminal metallic material layer.
6. The semiconductor electronic device according to claim 5 wherein said second upper terminal metallic material layer of said power pads has a thickness of more than 2 microns.
7. The semiconductor electronic device according to claim 6 wherein each upper terminal metallic layer of the signal pads is arranged at a lower level with respect to each second upper terminal layer of the power pads.
8. A semiconductor device comprising: a die of a semiconductor material; a support electrically connected to the die; a plurality of power pads, each power pad being separated from an adjacent power pad by a first pitch, said first pitch being defined as the shortest distance between two adjacent power pads; and a plurality of signal pads, each signal pad being separated from an adjacent signal pad by a second pitch, said second pitch being defined as the shortest distance between two adjacent signal pads; wherein, the first pitch is wider than the second pitch, and each power pad is higher than each signal pad.
9. The semiconductor device of claim 8 wherein said first pitch is equal or more than 90 microns, and said second pitch is less than 90 microns.
10. The semiconductor device according to claim 8 wherein said signal pads and said power pads are implemented in distinct regions of the die of semiconductor material.
11. The semiconductor device according to claim 8 wherein said signal pads have a multilayer structure comprising metallic layers alternated by insulating material layers and upperly ending with an upper terminal metallic material layer.
12. The semiconductor device according to claim 11 wherein said upper terminal metallic material layer of said signal pads has a thickness less than or equal to 2 microns.
13. The semiconductor device according to claim 8 wherein said power pads have a multilayer structure comprising first metallic layers alternated by insulating material layers and upperly ending with a second upper terminal metallic material layer.
14. The semiconductor device according to claim 13 wherein said second upper terminal metallic material layer of said power pads is more than 2 microns thick.
15. The semiconductor device according to claim 14 wherein each upper terminal metallic layer of the signal pads is arranged at a lower level with respect to each second upper terminal layer of the power pads.
16. A semiconductor device comprising: a die of semiconductor material; a plurality of first conductive stripes on a first region of the die, each first conductive stripe being separated from an adjacent one of the first conductive stripes by a first distance; a plurality of second conductive stripes on a second region of the die, each second conductive stripe being separated from an adjacent one of the second conductive stripes by a second distance; a plurality of insulating layers overlying each of the first and second conductive stripes; and a plurality of external conductive layers overlying the insulating layers that are overlying the first conductive stripes, wherein, the first distance is greater than the second distance, and each of the external conductive layer is more than 2 microns in thickness.
17. The semiconductor device of claim 16 wherein the first distance equals or is greater than 90 microns, and the second distance is less than 90 microns.
18. The semiconductor device of claim 16 wherein each of the first and second conductive stripes comprises a metallic material.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 9, 2004
October 24, 2006
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