Memory device capable of changing data output mode

1. A memory device, comprising: an address comparator in which a fail address used to select a fail cell is stored on an 8-bit output mode basis, wherein the address comparator compares an address signal and the fail address, and generates a repair enable signal if the address signal and the fail address coincide with each other; an address signal controller which transfers the address signal in entirety to the address comparator in the 8-bit output mode, and transfers address bits of the address signal that are used only in the 8-bit output mode as a given logic value, so that the transferred address bits are not compared in a 16-bit output mode according to an output mode decision signal and a 8-bit forced decision signal; and a fail bit signal generator that generates fail bit signals that indicate to which bit of output data does fail data of the fail cell correspond according to the repair enable signal, wherein although information on the fail address is stored on the 8-bit output mode basis, the memory device is configured to operate as the 8-bit output mode or the 16-bit output mode according to the output mode decision signal and the 8-bit forced decision signal.

2. The memory device of claim 1 , wherein the address comparator includes a plurality of fuses, wherein the fuses are selectively cut so that the fail address is stored, wherein the given logic value is High.

3. The memory device of claim 1 , wherein the address comparator comprises: a first switching element, which is connected between a power supply voltage terminal and a first node being an output node, and is configured to operate according to a first enable signal; a second switching element, which is connected to a ground voltage terminal and configured to operate according to a second enable signal; and a plurality of switching units in which a node and a switch component in which a transistor and a fuse are serially connected are connected in a parallel manner, the plurality of the switching units being serially connected between the first switching element and the second switching element, wherein the fuses are selectively cut according to the fail address, and bits of the address signal are input to the transistors included in the switching units, respectively, wherein the given logic value is High.

4. The memory device of claim 3 , wherein the transistor of the switch component comprises an NMOS transistor.

5. The memory device of claim 3 , wherein the first switching element comprises a PMOS transistor, and the second switching element comprises an NMOS transistor.

6. The memory device of claim 1 , wherein the address signal controller comprises: a first NAND gate configured to perform a NAND operation on the output mode decision signal and an inverted 8-bit forced decision signal; a second NAND gate configured to perform a NAND operation on the output signal of the first NAND gate and one of the address bits, thereby inverting the address bit in the 8-bit output mode, and outputting the address bit with the given logic value in the 16-bit output mode; an inverter configured to invert the output signal of the first NAND gate; and a NOR element configured to perform a NOR operation on the address bit input signal of the second NAND gate and the output signal of the inverter, the output of the NOR element passing the address bit information in entirety in the 8-bit output mode and the output being set to High in the 16-bit output mode.

7. The memory device of claim 1 , wherein the fail bit signal generator comprises: a switching element, which is connected between a power supply voltage terminal and a first node, and operates according to the repair enable signal; first to fourth switching components each connected between the first node and first to fourth output terminals; and fifth to eighth switching components each connected between a ground voltage terminal and the first to fourth output terminals, wherein each of the switching components has a structure in which fuses are selectively cut depending on which bits of the output data correspond to the fail data, and each of the switching components comprises a transistor which receives an inverted signal of the repair enable signal, wherein the switching element, the first to fourth switching components, and the fifth to eighth switching components are connected in a serial manner.

8. The memory device of claim 7 , wherein the switching element is a PMOS transistor, and each transistor of the switching components comprises an NMOS transistor.

9. The memory device of claim 1 , further comprising a fail bit signal controller configured to take a most significant bit of the fail signal, and produce an output when in 16-bit output mode, wherein the output of the most significant bit is set to Low when the 8-bit forced decision signal is set to 8-bit output mode.

10. The memory device of claim 9 , wherein the fail bit signal controller comprises: a transmitter that transmits the most significant bit of the fail signal according to the 8-bit forced decision signal; and a switching element, which is connected between an output terminal of the transmitter and a ground voltage terminal, and outputs the most significant bit as Low in the 8-bit output mode according to the 8-bit forced decision signal.

11. The memory device of claim 10 , wherein the switching element is an NMOS transistor.

12. The memory device of claim 1 , further comprising an I/O multiplexer which outputs the output data as 16 bits or 8 bits according to an address bit generated by the address signal controller, and outputs repair data of a redundancy array instead of outputting fail data according to the fail bit signal.

13. A memory device, comprising: a cell array including a plurality of cells, configured to output data according to an address signal; a redundancy array including a plurality of repair cells, configured to output repair data that will replace fail data output from a fail cell of the cell array according to the address signal; a fail bit detector in which a fail address used to select the fail cell is stored according to a first output mode, wherein the fail bit detector compares the address signal and the fail address in the first output mode according to an output mode decision signal and an m-bit forced decision signal, and compares an address bit located within an address signal used to signify a second output mode with the fail address, thus outputting a fail bit signal which indicates which bits are in error; and an I/O multiplexer configured to output the repair data instead of the fail data according to the fail bit signal, and output m bits of data in the first output mode, and output n bits of data in the second output mode, wherein information on the fail address is stored according to the first output mode, and the memory device is configured to operate in the first output mode or the second output mode according to the output mode decision signal and the m-bit forced decision signal.

14. The memory device of claim 13 , wherein the fail bit detector comprises: an address comparator in which the fail address is stored according to the first output mode, wherein the address comparator compares the address signal and the fail address, and generates a repair enable signal if the address signal and the fail address correspond to each other; an address signal controller, which transfers the address signal in entirety to the address comparator in the first output mode, and transfers address bits that are used only in the first output mode, among the address signal, the transferred address bits being set to a given logic value so that the address bits are not compared in the second output mode according to the output mode decision signal and the m-bit forced decision signal; and a fail bit signal generator that uses the repair enable signal to generate fail bit signals, which indicate which bits of the output data correspond to the fail data of the fail cell.

15. The memory device of claim 14 , wherein the first output mode is an 8-bit output mode and the second output mode is a 16-bit comparator, the address signal controller, and the fail bit signal generator are provided to match the number of columns of the redundancy array.

16. The memory device of claim 14 , wherein the address comparator includes a plurality of fuses, wherein the fuses are selectively cut so that the fail address is stored.

17. The memory device of claim 14 , wherein the address comparator comprises: a first switching element, which is connected between a power supply voltage terminal and a first node being an output node, and operates according to a first enable signal; a second switching element, which is connected to a ground voltage terminal and operates according to a second enable signal; and a plurality of switching units in which a first switch and a second switch in which a transistor and a fuse are serially connected are connected in a parallel manner, the plurality of the switching units being serially connected between the first switching element and the second switching element, wherein the fuses are selectively cut according to the fail address, and bits of the address signal are respectively input to the transistors of the switching units.

18. The memory device of claim 17 , wherein each transistor of the switching units comprises an NMOS transistor.

19. The memory device of claim 17 , wherein the first switching element comprises a PMOS transistor, and the second switching element comprises an NMOS transistor.

20. The memory device of claim 14 , wherein the address signal controller comprises: a first NAND gate configured to perform a NAND operation on the output mode decision signal and an inverted 8-bit forced decision signal; a second NAND gate configured to perform a NAND operation on the output signal of the first NAND gate and the address bit used to signify the first output mode, thereby inverting the address bit in the first output mode, and outputting the address bit as High in the second output mode; an inverter configured to invert the output signal of the first NAND gate; and a NOR element configured to perform a NOR operation on the input address bit signal of the second NAND gate and the output signal of the inverter, the output of the NOR element directly passing the address bit information to the address comparator in the first output mode and the output of the NOR element being set to High in the second output mode.

21. The memory device of claim 14 , wherein the fail bit signal generator comprises: a switching element, which is connected between a power supply voltage terminal and a first node, and operates according to the repair enable signal; first to fourth switches each connected between the first node and first to fourth output terminals; and fifth to eighth switches each connected between a ground voltage terminal and the first to fourth output terminals, wherein each of the switches has a structure in which fuses are selectively cut depending on which bits of the output data are in error, and each of the switches comprises a transistor which receives an inverted signal of the repair enable signal, wherein the switching element, the first to fourth switches, and the fifth to eighth switches are connected in a serial manner.

22. The memory device of claim 21 , wherein the switching element comprises a PMOS transistor, and the transistor of the switches comprises an NMOS transistor.

23. The memory device of claim 14 , further comprising a fail bit signal controller configured to output a most significant bit of the second output mode, wherein the most significant bit is set to Low when the m-bit forced decision signal is set to the first output mode.

24. The memory device of claim 23 , wherein the fail bit signal controller comprises: a transmitter that transmits the most significant bit of the fail signal according to the m-bit forced decision signal; and a switching element, which is connected between an output terminal of the transmitter and a ground voltage terminal, and outputs the most significant bit as Low in the first output mode according to the m-bit forced decision signal.

25. The memory device of claim 24 , wherein the switching element is an NMOS transistor.