A semiconductor device includes a data holding unit, a precharge unit and a delay unit. The data holding unit includes a plurality of memory cells. The precharge unit includes a precharge potential line, a precharge signal line and a plurality of switches. The delay unit includes a plurality of transistors. In addition, the semiconductor device can further include one or both of an address selecting unit having a column-decoder and a row-decoder and a display unit having a plurality of pixels. Reading and writing of data can be accurately performed by preventing malfunction even with a delay in a selection of an address.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising: a memory unit, comprising: a data holding unit having a plurality of memory cells; a precharge unit electrically connected to the data holding unit, having: a precharge potential line; a plurality of switches electrically connected to the precharge potential line; and a precharge signal line electrically connected to the plurality of switches; and a delay unit electrically connected to the precharge signal line, having a plurality of transistors; a control unit electrically connected to the memory unit; a power generation unit electrically connected to the memory unit and the control unit; and a transmit and receive unit electrically connected to the control unit.
2. The semiconductor device according to claim 1 , wherein each of the plurality of memory cells includes a memory element in a region where a bit line and a word line intersect each other through an insulator.
3. The semiconductor device according to claim 2 , wherein the memory element is one or complement selected among a transistor, a capacitor element or a resistor element.
4. The semiconductor device according to claim 2 , wherein the bit line is electrically connected to corresponding one of the plurality of switches.
5. The semiconductor device according to claim 1 , wherein each of the plurality of switches is a transistor or an analog switch.
6. The semiconductor device according to claim 1 , wherein input nodes of the delay unit are connected to a CK line and a WEB line; a CK line, a WEB line and a CEB line; an REB line and a WEB line; or an REB line, a WEB line and a CEB line.
7. The semiconductor device according to claim 1 , wherein the semiconductor device is selected from the group consisting of a DRAM, an SRAM, an FRAM, a masked ROM, a PROM, an EPROM, an EEPROM and a flash memory.
8. A semiconductor device comprising: a memory unit, comprising: a data holding unit having a plurality of memory cells; an address selecting unit electrically connected to the data holding unit, having a column-decoder and a row-decoder; a precharge unit electrically connected to the data holding unit, having: a precharge potential line; a plurality of switches electrically connected to the precharge potential line; and a precharge signal line electrically connected to the plurality of switches; and a delay unit electrically connected to the precharge signal line, having a plurality of transistors; a control unit electrically connected to the memory unit; a power generation unit electrically connected to the memory unit and the control unit; and a transmit and receive unit electrically connected to the control unit.
9. The semiconductor device according to claim 8 , wherein each of the plurality of memory cells includes a memory element in a region where a bit line and a word line intersect each other through an insulator.
10. The semiconductor device according to claim 9 , wherein the memory element is one or complement selected among a transistor, a capacitor element or a resistor element.
11. The semiconductor device according to claim 9 , wherein the bit line is electrically connected to corresponding one of the plurality of switches.
12. The semiconductor device according to claim 8 , wherein each of the plurality of switches is a transistor or an analog switch.
13. The semiconductor device according to claim 8 , wherein input nodes of the delay unit are connected to a CK line and a WEB line; a CK line, a WEB line and a CEB line; an REB line and a WEB line; or an REB line, a WEB line and a CEB line.
14. The semiconductor device according to claim 8 , wherein the semiconductor device is selected from the group consisting of a DRAM, an SRAM, an FRAM, a masked ROM, a PROM, an EPROM, an EEPROM and a flash memory.
15. A semiconductor device comprising: a memory unit, comprising: a data holding unit having a plurality of memory cells; a precharge unit electrically connected to the data holding unit, having: a precharge potential line; a plurality of switches electrically connected to the precharge potential line; and a precharge signal line electrically connected to the plurality of switches; and a delay unit electrically connected to the precharge signal line, having a plurality of transistors; a central processing unit electrically connected to the delay unit; a display unit electrically connected to the central processing unit, having a plurality of pixels; a control unit electrically connected to the memory unit; a power generation unit electrically connected to the memory unit and the control unit; and a transmit and receive unit electrically connected to the control unit.
16. The semiconductor device according to claim 15 , wherein each of the plurality of memory cells includes a memory element in a region where a bit line and a word line intersect each other through an insulator.
17. The semiconductor device according to claim 16 , wherein the memory element is one or complement selected among a transistor, a capacitor element or a resistor element.
18. The semiconductor device according to claim 16 , wherein the bit line is electrically connected to corresponding one of the plurality of switches.
19. The semiconductor device according to claim 15 , wherein each of the plurality of switches is a transistor or an analog switch.
20. The semiconductor device according to claim 15 , wherein input nodes of the delay unit are connected to a CK line and a WEB line; a CK line, a WEB line and a CEB line; an REB line and a WEB line; or an REB line, a WEB line and a CEB line.
21. The semiconductor device according to claim 15 , wherein the semiconductor device is selected from the group consisting of a DRAM, an SRAM, an FRAM, a masked ROM, a PROM, an EPROM, an EEPROM and a flash memory.
22. A semiconductor device comprising: a memory unit, comprising: a data holding unit having a plurality of memory cells; an address selecting unit electrically connected to the data holding unit, having a column-decoder and a row-decoder; a precharge unit electrically connected to the data holding unit, having: a precharge potential line; a plurality of switches electrically connected to the precharge potential line; and a precharge signal line electrically connected to the plurality of switches; and a delay unit electrically connected to the precharge signal line, having a plurality of transistors; a central processing unit electrically connected to the delay unit and the address selecting unit; a display unit electrically connected to the central processing unit, having a plurality of pixels; a control unit electrically connected to the memory unit; a power generation unit electrically connected to the memory unit and the control unit; and a transmit and receive unit electrically connected to the control unit.
23. The semiconductor device according to claim 22 , wherein each of the plurality of memory cells includes a memory element in a region where a bit line and a word line intersect each other through an insulator.
24. The semiconductor device according to claim 23 , wherein the memory element is one or complement selected among a transistor, a capacitor element or a resistor element.
25. The semiconductor device according to claim 23 , wherein the bit line is electrically connected to corresponding one of the plurality of switches.
26. The semiconductor device according to claim 22 , wherein each of the plurality of switches is a transistor or an analog switch.
27. The semiconductor device according to claim 22 , wherein input nodes of the delay unit are connected to a CK line and a WEB line; a CK line, a WEB line and a CEB line; an REB line and a WEB line; or an REB line, a WEB line and a CEB line.
28. The semiconductor device according to claim 22 , wherein the semiconductor device is selected from the group consisting of a DRAM, an SRAM, an FRAM, a masked ROM, a PROM, an EPROM, an EEPROM and a flash memory.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 23, 2004
October 31, 2006
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