Synchronous dynamic random access memory devices having dual data rate 1 (DDR1) and DDR2 modes of operation and methods of operating same

1. A synchronous dynamic random access memory device for both DDR 1 and DDR 2 mode operations, comprising: a mode selection circuit configured to generate a first mode selection signal that activates a DDR 1 mode operation and a second mode selection signal that activates a DDR 2 mode operation; a row decoder configure to decode a row address; a column decoder configured to select two global data lines for one unit data input/output in response to the first mode selection signal, and configured to select four global data lines for said one unit data input/output in response to the second mode selection signal; a core section configured to receive data from the two global data lines arid output the data to the two global data lines in response to the first mode selection signal, and configured to receive the data from the four global data lines and output the data to the four global data lines in response to the second mode selection signal; and an input and output control circuit configured to prefetch two bits data in response to the first mode selection signal to provide the two bits data to the core section, configure to output the two bits data received from the core section in response to the first mode selection signal, configured to prefetch four bits data in response to the second mode selection signal to provide the four bits data to the core section, and configured to output the four bits data received from the core section in response to the second mode selection signal.

2. A dual data rate dynamic random access memory (DDR DRAM) device comprising: a mode selection circuit configured to enable a Dual Data Rate (DDR) 1 mode of operation for the DDR DRAM or a DDR 2 mode of operation for the DDR DRAM.

3. A device according to claim 2 further comprising: a column decoder configured to select two global data lines in the DDR 1 mode responsive to a column address applied thereto and configured to select four global data lines in the DDR 2 mode responsive to the column address applied thereto.

4. A device according to claim 2 further comprising: a core section configured to send/receive data to/from the two selected global data lines in DDR 1 mode and configured to send/receive data to/from the four selected global data lines in DDR 2 mode.

5. A device according to claim 3 wherein the column decoder is configured to disregard one column address bit to enable two column select signals therefrom in DDR 1 mode and is configured to disregard two column address bits to enable four column select signals therefrom in DDR 2 mode.

6. A device according to claim 2 further comprising: an input latch configured to prefetch two data bits in DDR 1 mode and configured to prefetch four data bits in DDR 2 mode.

7. A device according to claim 6 wherein the input latch comprises: first and second serially coupled latches, wherein, if the DDR 2 mode is active, the input latch receives first, second, third and fourth data, the third and fourth data are latched by the first latch to be provided to an output of the input latch and the first and second data are by first and second latch to be provided to the output of the input Latch, and wherein, if the DDR 1 mode is active, the input latch receives fifth and sixth data, the fifth and sixth data are latched by the first latch to be provided to the output of the input latch.

8. A device according to claim 7 wherein the input latch is configured to provide the prefetched two bits to the output of the latch on the same clock edge in DDR 1 mode and configured to provide the prefetched four bits to the output of the latch on the same clock edge in DDR 2 mode.

9. A device according to claim 3 further comprising: an input ordering circuit configured to order prefetched two or four bits on outputs of the input ordering circuit based on values of the column address and the DDR 1 and DDR 2 mode.

10. A device according to claim 9 wherein the input ordering circuit is configured to reverse the order of the prefetched two bits in DDR 1 mode based on the column address; and wherein the input ordering circuit is configured to reverse the order of the prefetched four bits in DDR 2 mode based on the column address.

11. A device according to claim 10 further comprising: a connector circuit configured to couple ordered data provided from the input ordering circuit to global data I/O lines based on the DDR mode.

12. A device according to claim 3 further comprising: an output ordering circuit configured to order prefetched two or four bits output from the core section based on values of the column address and the DDR 1 and DDR 2 mode.

13. A device according to claim 12 wherein the output ordering circuit is configured to reverse the order of the prefetched two bits in DDR 1 mode based on the column address; and wherein the input ordering circuit is configured to reverse the order of the prefetched four bits in DDR 2 mode based on the column address.

14. A device according to claim 2 wherein the DDR 1 mode or the DDR 2 mode is selected via metal wiring, an MRS mode bit, and/or a fuse.

15. A method of operating a dual mode DDR DRAM device comprising: operating in a DDR 1 mode responsive to a first mode selection signal; and operating in a DDR 2 mode of operation responsive to a second mode selection signal.