Semiconductor integrated circuit

1. A semiconductor integrated circuit comprising: a delay circuit having a constant current source, a delay stage, and a compensating circuit; and a load transistor connected in parallel with the compensating circuit at a constant current node of the constant current source, wherein said delay stage determines an operation delay time of an output relative to an input depending on a constant current produced by the constant current source and said delay stage comprises inverter type circuits including a plurality of first transistors each having a mutual conductance determined by the constant current produced by the constant current source, and a plurality of second transistors switched in response to the input and arranged in series with the plurality of first transistors, and wherein a current that flows through the load transistor is mirror-reflected on the plurality of first transistors, wherein said compensating circuit compensates for a variation in delay characteristic of the delay stage due to at least one of a variation in temperature, a variation in power supply voltage, and a process variation.

2. A semiconductor integrated circuit comprising: a delay circuit having a constant current source, a delay stage, and a compensating circuit; and a load MOS transistor connected in parallel with the compensating circuit at a constant current node of the constant current source, wherein said delay stage determines an operation delay time of an output relative to an input depending on a constant current produced by the constant current source and said delay stage comprises complementary MOS inverter type circuits including a first plurality of transistors each having a mutual conductance determined by the constant current produced by the constant current source, and a second plurality of transistors switched in response to the input signal and arranged in series with the first plurality of transistors, and wherein a current that flows through the load transistor is mirror-reflected on the first plurality of transistors which are the same conduction type as the load MOS transistor, wherein said compensating circuit compensates for a variation in delay characteristic of the delay stage due to at least one of a variation in temperature, a variation in power supply voltage, and a process variation, wherein the first plurality of transistors includes p channel type current control MOS transistors and n channel type current control MOS transistors, and the second plurality of transistors includes p channel type switching MOS transistors and n channel type switching MOS transistors.

3. The semiconductor integrated circuit according to claim 2 , wherein the compensating circuit has a compensating element connected to the constant current node of the constant current source, and the compensating element is one MOS transistor identical in size to current control MOS transistors of one conduction type in each of the complementary MOS inverter type circuits.

4. The semiconductor integrated circuit according to claim 2 , wherein the compensating circuit has a compensating element connected to the constant current node of the constant source, and the compensating element is a MOS transistors equivalently smaller in size than the current control MOS transistors of one conduction type in the complementary MOS inverter type circuitse.

5. The semiconductor integrated circuit according to claim 4 , wherein the equivalently small-sized MOS transistors are equivalent to MOS transistors connected in series in plural form, which are identical in size to the current control MOS transistors of one conduction type in the complementary MOS inverter type circuits.

6. The semiconductor integrated circuit according to claim 2 , wherein the compensating circuit comprises a current mirror circuit which supplies a mirror current to the constant current node of the constant current source, and the current mirror circuit comprises p channel type MOS transistors identical in size to the p channel type current control MOS transistors in the complementary MOS inverter type circuits, and an n channel type MOS transistor identical in size to the n channel type current control MOS transistors in the complementary MOS inverter type circuits.

7. The semiconductor integrated circuit according to claim 6 , wherein the delay circuit is configured as a timing generator which delays the input at the delay stage to output a timing signal.

8. The semiconductor integrated circuit according to claim 7 , further comprising a memory equipped with the delay circuit, wherein the memory performs a read operation using the timing signal generated by the delay circuit.

9. The semiconductor integrated circuit according to claim 7 , further including a logic circuit which controls access to the memory.

10. The semiconductor integrated circuit according to claim 6 , wherein the delay circuit is configured as a ring oscillator which feeds back the output of the delay stage to the input thereof to generate a clock.

11. A semiconductor integrated circuit comprising: a delay circuit having a constant current source, a delay stage, and a compensating circuit; a load transistor connected in parallel with the compensating circuit at a constant current node of the constant current source; and a trimming register which loads trimming data therein, and a digital-to-analog converter which digital/analog-converts the trimming data loaded into the trimming register, wherein the constant current source has a MOS transistor of which the gate-to-source voltage is set in such a manner that a difference in current between the drain and source due to a difference in temperature becomes small, wherein a voltage outputted from the digital-to-analog converter defines a gate voltage to be applied to the MOS transistor of the constant current source, wherein said delay stage determines an operation delay time of an output relative to an input depending on a constant current produced by the constant current source and said delay stage comprises inverter type circuits including a first plurality of transistors each having a mutual conductance determined by the constant current produced by the constant current source, and a second plurality of transistors switched in response to the input signal and arranged in series with the first plurality of transistors, wherein a current that flows through the load transistor is mirror-reflected on the first plurality of transistors, and wherein said compensating circuit compensates for a variation in delay characteristic of the delay stage due to at least one of a variation in temperature, a variation in power supply voltage, and a process variation.

12. The semiconductor integrated circuit according to claim 11 , further comprising a non-volatile memory area which holds trimming data, and a control circuit which reads the trimming data from the non-volatile memory area in response to a reset and loads the trimming data into the trimming register.