Page buffer circuit of flash memory device with reduced consumption power

1. A page buffer of a flash memory device, comprising a bitline selection circuit connecting one of at least two bitlines to a sensing node in response to bitline selection signals; a cache register circuit storing a program data signal during a programming operation; a main register circuit storing a first state data signal corresponding to a read data signal received from one of the two bitlines through the sensing node in a reading operation, in response to a main latch signal, or storing a second state data signal corresponding to the program data signal received from the cache register circuit through the sensing node in a programming operation; and a power supply circuit providing first and second voltages to the main register circuit and the cache register circuit as operation voltages in an active mode, and providing a third voltage to the main register circuit and the cache register circuit as operation voltages in a standby mode.

2. The page buffer of a flash memory device as set forth in claim 1 , which further comprises: a precharge circuit charging the sensing node up to a predetermined voltage level in response to a precharge control signal; a first switch transferring the program data signal from the cache register circuit to the main register circuit through the sensing node in the programming operation, in response to a first control signal, and disconnecting the cache register circuit from the sensing node in the reading operation; a second switch transferring an inverse data signal of the second state data signal from the main register circuit to one of the two bitlines connected to the sensing node through the bitline selection circuit in a second control signal during the programming operation; and a third switch transferring an inverse data signal of the first state data signal from the main register circuit to a Y-gate circuit in response to a third control signal during the reading operation.

3. The page buffer of a flash memory device as set forth in claim 1 , wherein the third voltage is lower than the first voltage and higher than the second voltage.

4. The page buffer of a flash memory device as set forth in claim 1 , wherein the main register circuit comprises: a sensing circuit generating the first state data signal in response to the main latch signal and the read data signal, or generating the second state data signal in response to the main latch signal and the program data signal; a main latch circuit, connected to the sensing circuit through a first node, holding the first or second state data signal received through the first node and transferring an inverse data signal of the first state data signal or an inverse data signal of the second state data signal to a second node; and a main latch rest circuit initializing the main latch circuit in response to a main latch reset signal, wherein the first and second nodes have different voltage levels from each other in the active mode, while the first and second nodes have the same voltage level in the standby mode.

5. The page buffer of a flash memory device as set forth in claim 4 , wherein the cache register circuit comprises: a cache latch circuit, connected between a third node and a fourth node, holding the program data signal received through the third node and transferring an inverse data signal of the program data signal to the fourth node, or holding the program data signal and transferring the inversed data signal of the program data signal to the third node; and a cache latch rest circuit, connected to the cache latch circuit through the third node, initializing the cache latch circuit in response to a cache latch reset signal, wherein the third and fourth nodes have different voltage levels from each other in the active mode, while the third and fourth nodes have the same voltage level in the standby mode.

6. The page buffer of a flash memory device as set forth in claim 5 , wherein the main latch circuit comprises: a first inverter having an output terminal connected to the first node and an input terminal connected to the second node, receiving the operation voltages through fifth and sixth nodes; and a second inverter having an input terminal connected to the first node and an output terminal connected to the second node, receiving the operation voltages through the fifth and sixth nodes, wherein the cache latch circuit comprise: a third inverter having an output terminal connected to the third node and an input terminal connected to the fourth node, receiving the operation voltages through seventh and eighth nodes; and a fourth inverter having an input terminal connected to the third node and an output terminal connected to the fourth node, receiving the operation voltages through the seventh and eighth nodes.

7. The page buffer of a flash memory device as set forth in claim 6 , wherein the power supply circuit comprises: a first switch connected among the fifth node, the seventh node, and the first voltage, and being turned on or off in response to a first selection control signal; a second switch connected among the sixth node, the eighth node, and the second voltage, and being turned on or off in response to the first selection control signal; a third switch connected among the fifth node, the seventh node, and the third voltage, and being turned on or off in response to a second selection control signal; and a fourth switch connected among the sixth node, the eighth node, and the third voltage, and being turned on or off in response to the second selection control signal.

8. The page buffer of a flash memory device as set forth in claim 7 , wherein in the active mode, the first selection control signal is enabled while the second selection is disabled, and in the standby mode, the first selection control signal is disabled while the second selection is enabled, wherein the first and second switches are turned on when the first selection control signal is enabled, while the third and fourth switches are turned on when the second selection control signal is enabled.