A silicon-on-insulator semiconductor device which includes a substrate; and insulator layer overlying the substrate; a plurality of strained silicon islands overlying the insulator layer, the strained silicon islands are isolated from each other by mesa isolation; and a plurality of transistors formed on the strained silicon islands. A method for fabricating the silicon-on-insulator semiconductor device is further disclosed.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A silicon-on-insulator semiconductor device comprising: a substrate; an insulator layer overlying said substrate; a plurality of strained silicon islands comprising internally strained silicon on and completely overlying said insulator layer, said strained silicon islands having a tensile stress in the plane of the substrate with a magnitude between 0.1% and 2% and, said strained silicon islands isolated from each other by mesa isolation; and a plurality of transistors formed on said strained silicon islands.
2. The silicon-on-insulator semiconductor device of claim 1 , wherein said substrate comprises a semi-conducting material.
3. The silicon-on-insulator semiconductor device of claim 1 , wherein said substrate comprises a silicon wafer.
4. The silicon-on-insulator semiconductor device of claim 1 , wherein said insulator layer comprises a dielectric.
5. The silicon-on-insulator semiconductor device of claim 1 , wherein said insulator layer comprises silicon oxide.
6. The silicon-on-insulator semiconductor device of claim 1 , wherein said strained silicon islands have thicknesses in the range of between 10 Angstroms and 500 Angstroms.
7. The silicon-on-insulator semiconductor device of claim 1 , wherein said strained silicon islands comprise rounded corners at isolation edges.
8. A silicon-on-insulator semiconductor device comprising: a substrate; an insulator layer overlying said substrate; a plurality of strained silicon islands comprising internally strained silicon on and completely overlying said insulator layer, said strained silicon islands having a stress in the plane of the substrate, said strained silicon islands isolated from each other by mesa isolation; and a plurality of transistors formed on said strained silicon islands.
9. The silicon-on-insulator semiconductor device of claim 8 , wherein said stress comprises a tensile stress.
10. The silicon-on-insulator semiconductor device of claim 8 , wherein said stress has a magnitude of between about 0.1% and 2%.
11. The silicon-on-insulator semiconductor device of claim 8 , wherein said substrate comprises a semiconducting material.
12. The silicon-on-insulator semiconductor device of claim 8 , wherein said substrate comprises a silicon wafer.
13. The silicon-on-insulator semiconductor device of claim 8 , wherein said insulator layer comprises a dielectric.
14. The silicon-on-insulator semiconductor device of claim 8 , wherein said insulator layer comprises silicon oxide.
15. The silicon-on-insulator semiconductor device of claim 8 , wherein said strained silicon islands have thicknesses in the range of between 10 Angstroms and 500 Angstroms.
16. The silicon-on-insulator semiconductor device of claim 8 , wherein said strained silicon islands comprise rounded corners.
17. A silicon-on-insulator semiconductor device comprising: a semiconductor substrate; an insulator layer overlying said semiconductor substrate; a plurality of strained silicon islands comprising internally strained silicon on and completely overlying said insulator layer, said strained silicon islands having a stress in the plane of the substrate, said strained silicon islands isolated from each other by mesa isolation; wherein said strained silicon islands comprise rounded corners; and a plurality of transistors formed on said strained silicon islands.
18. The silicon-on-insulator semiconductor device of claim 17 , wherein said stress comprises a tensile stress.
19. The silicon-on-insulator semiconductor device of claim 17 , wherein said stress has a magnitude of between about 0.1% and 2%.
20. The silicon-on-insulator semiconductor device of claim 17 , wherein said strained silicon islands have thicknesses in the range of between 10 Angstroms and 500 Angstroms.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 31, 2003
January 2, 2007
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