How to record and play back data at a high line density. A DSV control bit determining/inserting unit 11 inserts DSV control bits for execution of DSV control into an input data string and outputs the data string including the DSV control bits to a modulation unit 12. The modulation unit 12 converts the data string with a basic data length of 2 bits into variable length code with a basic code length of 3 bits in accordance with a conversion table and outputs the code resulting from the conversion to a NRZI encoding unit 13. The conversion table used by the modulation unit 12 includes substitution codes for limiting the number of consecutive appearances of a minimum run to a predetermined value and substitution codes for keeping a run length limit. In addition, the conversion table enforces a conversion rule, according to which the remainder of division of the “1” count of an element in a data string by 2 having a value of 0 or 1 shall always be equal to the remainder of division of the “1” count of an element in the code resulting from conversion of the data string by 2.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A modulation apparatus for converting data into variable length strings of channel bits that are NRZI representations of logical code words in which d is a minimum run length and k is a maximum run length limit of ‘0’ bits, said modulation apparatus having conversion means for converting input data into code in accordance with a conversion table wherein said conversion table enforces a conversion rule, according to which the remainder of division of a ‘1’ count of an element in a data string by 2 having a value of 0 or 1 shall always be equal to the remainder of division of a ‘1’ count of an element in the string of code words resulting from conversion of said data string by 2 and conversion codes of said conversion table comprise: basic codes; first substitution codes used when the basic codes fail to maintain the minimum run length d; and second substitution codes used when the basic codes fail to maintain the maximum run length limit k.
2. A modulation apparatus according to claim 1 characterized in that there are four basic codes that each convert two bit strings of data into three bit strings of channel bits.
3. A modulation apparatus according to claim 1 characterized in that said basic codes of said conversion tables have a variable length structure.
4. A modulation apparatus according to claim 1 characterized in that said basic codes of said conversion tables include a code ‘*0*’ wherein the symbol * is an indeterminate code which is ‘0’ if an immediately preceding or succeeding code word is ‘1’ and ’ 1 ′ if said immediately preceding or succeeding code word is ‘0’, implying that said code ‘*0*’ is either ‘000’ or ’ 101 ′.
5. A modulation apparatus according to claim 1 characterized in that said conversion codes of said conversion tables include codes each determined by referring to an immediately succeeding string of code words or an immediately succeeding data string.
6. A modulation apparatus according to claim 1 characterized in that said conversion codes of said conversion tables include codes each determined by referring to an immediately succeeding string of code words or a string of code words of a specific type.
7. A modulation apparatus according to claim 5 characterized in that said codes each determined by referring to an immediately succeeding string of code words or an immediately succeeding data string is said first or second substitution codes.
8. A modulation apparatus according to claim 1 characterized in that the number of pairs each comprising a data string and a code string composing said basic codes for a constraint length i of 1 is equal to 4 (=2^m=2^2).
9. A modulation apparatus according to claim 1 characterized in that, for constraint lengths i of 2 and greater, said conversion codes are all said first and second substitution codes.
10. A modulation apparatus according to claim 1 characterized in said conversion codes for a constraint length i of 2 are codes for keeping said minimum run d at 1.
11. A modulation apparatus according to claim 1 characterized in that said conversion codes of said conversion tables include codes each determined by referring to an immediately preceding string of code words.
12. A modulation apparatus according to claim 1 characterized in that said apparatus further has a synchronization signal inserting means for inserting a synchronization signal including a unique pattern not included in said conversion codes of said conversion table into any arbitrary position in said string of code words.
13. A modulation apparatus according to claim 10 characterized in that said unique pattern is a pattern that breaks said maximum run k.
14. A modulation apparatus according to claim 10 characterized in that said unique pattern is a pattern that keeps said minimum run d.
15. A modulation apparatus according to claim 10 characterized in that a unique pattern in said synchronization signal comprises 1 code word at the head thereof serving as a connection bit with a code word resulting from conversion of up to immediately preceding data, a second bit for keeping said minimum run d and a third bit.
16. A modulation apparatus according to claim 10 characterized in that said synchronization signal is at least 12 code words in size.
17. A modulation apparatus according to claim 10 characterized in that, for a synchronization signal of at least 21 code words in size, said synchronization signal includes at least 2 patterns with a maximum run k of 8.
18. A modulation apparatus according to claim 10 characterized in that said conversion codes of said conversion table include termination codes each for terminating said code resulting from conversion.
19. A modulation apparatus according to claim 16 characterized in that said termination codes are prescribed for said basic codes with a constraint length i, for which the number of pairs each comprising a data string and a code string composing said basic codes is smaller than 4 (=2^m=2^2), and enforce a conversion rule, according to which the remainder of division of a ‘1’ count of an element in a data string by 2 having a value of 0 or 1 shall always be equal to the remainder of division of a ‘1’ count of an element in the string of code words resulting from conversion of said data string by 2.
20. A modulation apparatus according to claim 16 characterized in that, in order to identify said termination code, 1 code word at the head of said synchronization signal pattern serving as a connection bit is set at ‘1’ when said termination code is used and at ‘0’ when said termination code is not used.
21. A modulation apparatus according to claim 10 characterized in that said unique pattern is sandwiched by 3 bits at the head of said synchronization signal and 3 bits at the tail of said synchronization signal and said 3 bits at said head and 3 bits at said tail are each used as a junction comprising mixed data and connection bits.
22. A modulation apparatus according to claim 10 characterized in that: the leading first one of 3 bits at the head of said synchronization signal has a value representing data words prior to conversion viewed in m-bit units; the next second one of said 3 bits is set at ‘1’ to prescribe said synchronization signal; the leading first one of 3 bits at the tail of said synchronization signal is set at ‘0’ to prescribe said synchronization signal; and the next second one of said 3 bits at said tail has a value representing said data words prior to conversion viewed in m-bit units.
23. A modulation apparatus according to claim 1 characterized in that said apparatus further has DSV control means for controlling a DSV of input data and supplying said DSV to said conversion means.
24. A modulation apparatus according to claim 1 characterized in that said conversion means comprises: a first code detecting means for detecting said first substitution codes for limiting the number of consecutive appearances of said minimum run d; and a second code detecting means for detecting said second substitution codes for keeping run length limit.
25. A modulation method to be adopted in a modulation apparatus for converting data into variable length strings of channel bits that are NRZI representations of logical code words in which d is a minimum run length and k is a maximum run length limit of ‘0’ bits, said modulation method including a converting input data into strings of channel bits in accordance with a conversion table wherein said conversion table enforces a conversion rule, according to which the remainder of division of a ‘1’ count of an element in a data string by 2 having a value of 0 or 1 shall always be equal to the remainder of division of a ‘1’ count of an element in the string of code words resulting from conversion of said data string by 2 and conversion codes of said conversion table comprise: basic codes for; first substitution codes used when the basic codes fail to maintain the minimum run length d; and second substitution codes used when the basic codes fail to maintain the maximum run length limit k.
26. A program presenting medium for presenting a program implementing processing including a conversion step of converting input data into code in accordance with a conversion table data in a modulation apparatus for converting data with a basic data length of m bits into variable length code (d, k; m, n; r) with a basic code length of n bits where d is a minimum run and k is a run length limit, said program presenting medium characterized in that said conversion table enforces a conversion rule, according to which the remainder of division of a ‘1’ count of an element in a data string by 2 having a value of 0 or 1 shall always be equal to the remainder of division of a ‘1’ count of an element in the string of code words resulting from conversion of said data string by 2 and conversion codes of said conversion table comprise: basic codes for d=1, k=7, m=2 and n=3; first substitution codes for limiting the number of consecutive appearances of said minimum run d; and second substitution codes for keeping said run length limit k.
27. A demodulation apparatus for converting variable length code (d, k; m, n; r) with a basic code length of n bits into data with a basic data length of m bits where d is a minimum run and k is a run length limit, said demodulation apparatus characterized by having conversion means for converting input code into data in accordance with a conversion table wherein said conversion table enforces a conversion rule, according to which the remainder of division of a ‘1’ count of an element in a data string by 2 having a value of 0 or 1 shall always be equal to the remainder of division of a ‘1’ count of an element in the string of code words resulting from conversion of said data string by 2 and conversion codes of said conversion table comprise: basic codes for d=1, k=7, m=2 and n=3; first substitution codes for limiting the number of consecutive appearances of said minimum run d; and second substitution codes for keeping said run length limit k.
28. A demodulation apparatus according to claim 25 characterized in that said apparatus further has a bit removing means for removing redundant bits inserted at predetermined intervals into said code.
29. A demodulation apparatus according to claim 26 characterized in that said redundant bits are DSV bits or synchronization signals.
30. A demodulation method to be adopted in a demodulation apparatus for converting variable length code (d, k m, n; r) with a basic code length of n bits into data with a basic data length of m bits where d is a minimum run (and k is a run length limit?), said modulation method characterized by having a conversion step of converting input code into data in accordance with a conversion table wherein said conversion table enforces a conversion rule, according to which the remainder of division of a ‘1’ count of an element in a data string by 2 having a value of 0 or 1 shall always be equal to the remainder of division of a ‘1’ count of an element in the string of code words resulting from conversion of said data string by 2 and conversion codes of said conversion table comprise: basic codes for d=1, k=7, m=2 and n=3; first substitution codes for limiting the number of consecutive appearances of said minimum run d; and second substitution codes for keeping said run length limit k.
31. A program presenting medium for presenting a program including a conversion step of converting input code into data in accordance with a conversion table in a demodulation apparatus for converting variable length code (d, k; m, n; r) with a basic code length of n bits into data with a basic data length of m bits where d is a minimum run and k is a run length limit, said program presenting medium characterized in that said conversion table enforces a conversion rule, according to which the remainder of division of a ‘1’ count of an element in a data string by 2 having a value of 0 or 1 shall always be equal to the remainder of division of a ‘1’, count of an element in the string of code words resulting from conversion of said data string by 2 and conversion codes of said conversion table comprise: basic codes for d=1, k=7, m=2 and n=3; first substitution codes for limiting the number of consecutive appearances of said minimum run d; and second substitution codes for keeping said run length limit k.
32. The modulation apparatus of claim 1 wherein said basic codes of said conversion table include a code ‘*0*’ and wherein the symbol * in ‘*0*’ stands for ‘0’ if an immediately preceding code bit is ‘1’ and stands for ‘1’ if said immediately preceding code bit is ‘0’, such that said code ‘*0*’ is either ‘000’ or ‘101’.
33. The modulation apparatus of claim 1 , wherein said conversion codes of said conversion table include codes each determined by referring to an immediately succeeding string of code words or an immediately succeeding data string.
34. The modulation apparatus of claim 31 , wherein data “11 01 11” is always converted to code bits “001 000 000” when the next portion of data are converted to code bits beginning with “010”.
35. The modulation apparatus of claim 1 , wherein: the basic codes are: “11” is converted to “*0*” where “*” is “1” when the last bit of the preceding code word is “1” and “*” is “0” when the last bit of the preceding code word is “001”; “10” is converted to “001”; 01” is converted to “010”; “00 11” is converted to “010 100”; “00 10” is converted to “010 000”: “00 01” is converted to “000 100”; “00 00 11” is converted to “000 100 100”; “00 00 10” is converted to “000 100 000”; “00 00 01” is converted to “010 100 100”; “00 00 00” is converted to “010 100 000”; the first substitution codes are: “11 01 11” is converted to “001 000 000” only when the following code word is “010”; the second substitution codes are: “00 00 10 00” is converted to “000 100 100 100”; “00 00 00 00” is converted to “010 100 100 100”.
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January 19, 2006
January 2, 2007
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