A flip chip package structure and manufacturing method thereof is provided. A chip is electrically connected to a substrate. A heat sink is attached to the backside of the chip. The heat sink has at least a through hole located at a peripheral region and laterally adjacent to the chip. A dispensing process is carried out to deliver an underfill material via the through hole such that the space between the chip and the substrate is filled. The underfill material also extends to cover a portion of the heat sink so that the heat sink and the substrate are connected together. The underfill material is cured to fix the heat sink, the substrate and the chip in position.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of fabricating a flip chip package, comprising the steps of: providing a substrate; connecting a chip to the substrate, wherein the chip comprises an active surface and a corresponding backside and the active surface comprises a plurality of bumps such that the chip and the substrate are electrically connected through the bumps; attaching a heat sink to the backside of the chip, wherein the heat sink comprises at least a through hole located outside a perimeter of the chip, and has a size significantly larger than a size of the chip; performing a dispensing process via the through hole by injecting an underfill material into a space between the active surface of the chip and the substrate, wherein a space between the heat sink and the substrate is not completely filled by the underfill material; and curing the underfill material to fix the substrate and the chip.
2. The method of claim 1 wherein the dispensing process comprises passing a dispensing needle through the through hole to deliver the underfill material to the space between the chip and the substrate as well as the heat sink.
3. The method of claim 1 , wherein the through hole is positioned outside the perimeter of the chip and adjacent to the chip.
4. The method of claim 1 , wherein the heat sink has a coefficient of thermal expansion comparable to the substrate.
5. The method of claim 1 , wherein the heat sink comprises an upper surface and a lower surface, and wherein the lower surface further comprises at least a stopper on an outer edge of the through hole.
6. The method of claim 1 , wherein before the step of attaching the heat sink to the chip, further comprises applying a thermal conductive layer to the backside of the chip.
7. The method of claim 1 , wherein the underfill material comprises epoxy resin.
8. The method of claim 7 , wherein the epoxy resin comprises a thermal-setting epoxy resin.
9. The method of claim 1 , wherein the step of performing the dispensing process further comprises injecting the underfill to cover a portion of the heat sink to connect the substrate and the heat sink.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 17, 2004
January 16, 2007
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.