The invention, which relates to a method for fabricating metallic interconnects with copper-nickel-gold layer construction on electronic components, is based on the object of specifying a method by means of which it is possible to fabricate such metallic interconnects on different electronic components cost-effectively by means of the known and tried and tested methods which have a comprehensive corrosion protection. According to the invention, the object is achieved by virtue of the fact that the interconnects are embodied such that they are completely encapsulated by being deposited in a manner buried in a patterned dielectric layer in the lower region and being covered in the upper region by a nickel-gold layer adjoining the lower encapsulation without any gaps.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of forming interconnects over an electronic component, the method comprising: providing an electronic component having contact areas overlying a surface thereof; forming a dielectric mask over the surface of the electronic component, the dielectric mask exposing portions of the surface of the electronic component; forming a first conductive layer over the dielectric mask and over the exposed portions of the surface of the electronic component; forming a resist mask over the first conductive layer, the resist mask including opening exposed portions of the first conductive layer over the exposed portions of the surface of the electronic component; selectively forming a conductor over the exposed portions of the first conductive layer; widening the openings in the resist mask; forming a second conductive layer over the conductor; removing the resist mask; and removing portions of the first conductive layer over the dielectric mask.
2. The method of claim 1 wherein the first conductive layer comprises a copper seed layer and wherein selectively forming a conductor comprises electroplating copper.
3. The method of claim 2 and further comprising forming a diffusion barrier over the dielectric mask and over the exposed portions of the surface of the electronic component, wherein the first conductive layer is formed over the diffusion barrier.
4. The method of claim 3 wherein the diffusion barrier comprises titanium.
5. The method of claim 2 wherein forming a first conductive layer comprises sputtering copper.
6. The method of claim 2 wherein forming a second conductive layer comprises forming a nickel layer over the copper and forming a gold layer over the nickel layer.
7. The method of claim 2 wherein the copper seed layer has a thickness in the range of approximately 120 to 180 nm.
8. The method of claim 7 wherein the copper seed layer has a thickness of approximately 150 nm.
9. The method claim 2 wherein forming a dielectric mask comprises using a lithography mask and wherein forming a resist mask comprises the same lithography mask.
10. The method of claim 9 wherein widening the openings comprises using a second lithography mask.
11. The method of claim 1 wherein the electronic component comprises a semiconductor component.
12. The method of claim 1 wherein the electronic component comprises a polymer component.
13. A method for fabricating metallic interconnects with copper-nickel-gold layer construction on an electronic component, the copper core of the interconnects being electrodeposited on a copper seed layer with a diffusion barrier arranged underneath and being covered by a nickel-gold layer by means of a resist mask, the method comprising: fabricating a dielectric mask on a surface of the component such that a mask structure encompasses the structure of the interconnects to be fabricated; applying a diffusion barrier and then a copper seed layer over the component, the diffusion barrier and copper seed layer overlying the mask structure; fabricating a resist mask on the copper seed layer by first lithographic patterning of the positive resist by means of a first lithography mask, the copper seed layer remaining free in the region of the interconnects to be fabricated; electrodepositing a copper core of the interconnects on the uncovered copper seed layer; patterning of the resist mask by means of a second lithography mask so that the mask openings of the resist mask that enclose the copper core of the interconnect are widened; applying a nickel-gold layer to the copper core; stripping the resist mask; and etching the diffusion barrier and the copper seed layer.
14. The method for fabricating metallic interconnects according to claim 13 , wherein the copper seed layer has a thickness in the range of approximately 120 to 180 nm.
15. The method for fabricating metallic interconnects according to claim 14 , wherein the copper seed layer has a thickness of approximately 150 nm.
16. The method for fabricating metallic interconnects according to claim 13 , wherein the dielectric mask and the resist mask are patterned lithographically using the same lithography mask.
17. The method for fabricating metallic interconnects according to claim 13 , wherein the diffusion barrier comprises titanium.
18. The method for fabricating metallic interconnects according to claim 13 , wherein applying a diffusion barrier and then a copper seed layer comprises sputtering the diffusion barrier and then sputtering the copper seed layer.
19. The method for fabricating metallic interconnects according to claim 13 , wherein the electronic component comprises a semiconductor component.
20. The method for fabricating metallic interconnects according to claim 13 , wherein the electronic component comprises a polymer component.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 28, 2005
February 6, 2007
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