An integrated circuit and a method of manufacturing the integrated circuit, the method including: (a) providing a substrate; (b) forming a copper diffusion barrier layer on the substrate; (c) forming a dielectric layer on a top surface of the copper diffusion barrier layer; (d) forming a copper damascene or dual damascene wire in the dielectric layer, a top surface of the copper damascene or dual damascene wire coplanar with a top surface of the dielectric layer; (e) forming a first capping layer on the top surface of the wire and the top surface of the dielectric layer; (f) after step (e) performing one or more characterization procedures in relation to said integrated circuit; and (g) after step (e) forming a second capping layer on a top surface of the first capping layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of manufacturing an interconnect, comprising: (a) providing a substrate; (b) forming a dielectric layer on said substrate; (c) forming a wire in said dielectric layer, a top surface of said wire coplanar with a top surface of said dielectric layer; (d) forming a first capping layer on said top surface of said wire and said top surface of said dielectric layer, (e) pushing a conductive probe tip through said first capping layer in order to make electrical contact to said wire, and then afterwards removing said conductive probe tip from said wire and said first capping layer; (f) after step (e) forming a second capping layer on a top surface of said first capping layer; and between steps (e) and (f), cleaning said top surface of said first capping layer.
2. The method of claim 1 , wherein said wire includes copper exposed to an ambient atmosphere at said top surface of said wire.
3. The method of claim 2 , wherein said first capping layer prevents formation, on said top surface of said wire, of copper containing particles by reaction of said wire with said dielectric layer.
4. The method of claim 1 , wherein said dielectric layer comprises fluorinated silicon glass.
5. The method of claim 4 , wherein said dielectric layer comprises about 1% to about 9% by weight of fluorine.
6. The method of claim 4 , wherein said wire includes copper exposed to an ambient atmosphere at said top surface of said wire.
7. The method of claim 6 , wherein said first capping layer prevents formation, on said top surface of said wire, of copper containing particles by reaction of copper in said wire with fluorine in said dielectric layer.
8. The method of claim 1 , wherein said first capping layer and said second capping layer independently include a material selected from the group consisting of Si x N y , Si x C y , SiC x H y , SiC x O y N z and SiC x N y .
9. The method of claim 1 , wherein said first capping layer and said second capping layer each include two or more layers, each layer of said two or more layers of said first and second capping layers independently including materials selected from the group consisting of Si x N y , Si x C y , SiC x H y , SiC x O y N z and SiC x N y .
10. The method of claim 1 , wherein said first capping layer has a thickness between about 100 Å and 300 Å.
11. The method of claim 1 , wherein said second capping layer has a thickness between about 150 Å and 700 Å.
12. The method of claim 1 , wherein said second capping layer is a copper diffusion barrier.
13. The method of claim 1 , wherein said first capping layer in combination with said second capping layer is a copper diffusion barrier.
14. The method of claim 1 , further including: (g) forming another dielectric layer on a top surface of said second capping layer, said second capping layer acting as a reactive ion etch stop for etching said another dielectric layer.
15. The method of claim 1 , wherein forming said first capping layer comprises forming silicon nitride by high density plasma deposition and forming said second capping layer comprises forming silicon nitride formed by plasma enhanced chemical vapor deposition.
16. The method of claim 1 , further including between steps and (e) (f), cryogenically cleaning said top surface of said first capping layer.
17. The method of claim 1 , further including between steps (c) and (d), cleaning said top surface of said wire and said top surface of said dielectric layer in a reducing environment.
18. The method of claim 1 , further including between steps (e) and (f), performing one or more characterization procedures selected from the group consisting of optical or SEM inspection and optical or SEM image size measurement.
19. The method of claim 1 , wherein said first capping layer is transparent to visible light, to back-scattered electrons in a SEM or to both.
20. The method of claim 1 , wherein said second capping layer is formed at a temperature of about 350° C. or greater.
21. The method of claim 1 , wherein said wire comprises copper and said dielectric layer comprises fluorinated silicon glass, said first capping layer preventing formation, on said top surface of said wire, of copper oxy fluoride particles by reaction of said wire with said dielectric layer.
22. The method of claim 1 , wherein said wire comprises copper and said dielectric layer comprises fluorinated silicon glass, said first capping layer preventing formation, on said top surface of said wire, of N x H y F z containing particles by reaction of said wire with said dielectric layer.
23. The method of claim 1 , further including between steps (e)b and (f), cryogenically cleaning said top surface of said first capping layer by spraying said top surface of first capping layer with particles of CO 2 , Ar or N 2 .
24. The method of claim 1 , wherein said first capping layer and said second capping layer independently include a material selected from the group consisting of SiC x H y , SiC x O y N z and SiC x N y .
25. The method of claim 1 , further including between steps (c) and (d), cleaning said top surface of said wire and said top surface of said dielectric layer in reducing plasma environment.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 20, 2004
February 13, 2007
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