Circuits and related methods for switched step-down and boost DC-to-DC converters have been achieved. Said DC-to-DC converters comprise an inductor current sensing and limiting circuit to prevent the inductor current to exceed a defined limit. Said current sense circuit is using the voltage on the on-state source-to-drain resistance of a power switch to monitor the inductor current. Said voltage is amplified and serves as input of a regulator. Said regulator, being connected via one or more gate controllers to the gates of said power switches, controls the ON/OFF state of said power switches by pulse-width-modulation. Said power switches are switched ON/OFF if the current exceeds a defined limit. After a defined time period said power switches are switched on again. Gate controllers keep the power switch in an operating region having a stable source-to-drain resistance while said power switch is ON. The ON/OFF duty cycle of said power transistor switches is set in a way that the difference between charge/discharge energy is kept on a minimum.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A current-limiting step-down DC-to-DC power converter, comprising: a high-side power switch connected to an input voltage source and to an inductor; a low side power switch connected to ground and to said inductor; an amplifying means to amplify the voltage on the on-state source-to-drain resistance of said high-side power switch as input to a regulator; a regulator having an input and an output, wherein the input is said amplified voltage and the output are signals to a gate controller setting said high-side power switch and said low-side power switch ON or OFF preventing the current through said inductor to exceed a limit and to achieve a duty cycle keeping the difference between charge/discharge energy to a minimum; a capacitor being connected on one side to ground and on the other side to an output port and to said inductor; said inductor being connected on one side to said high-side power switch and to said low-side power switch and on the other side to an output port; and a gate controller to control the gate voltages of each of said high-side power switch and low-side power switch having as input signals from said control unit.
2. The power converter circuit of claim 1 wherein said low-side power switch is a NMOS transistor.
3. The power converter circuit of claim 1 wherein said high-side power switch is a PMOS transistor.
4. The power converter circuit of claim 1 wherein said regulator is controlling the setting of power switches by pulse-width modulation signals.
5. The power converter circuit of claim 1 wherein said gate controller is setting the gate voltage below the threshold voltage of said power switches if they are put into an OFF state.
6. The power converter circuit of claim 1 wherein said gate controller is setting the gate voltage of said power switches in a way that said power switches operate in the linear ohmic region if they are put into an ON state.
7. The power converter circuit of claim 6 wherein said gate controller is setting the gate voltage three times the threshold voltage of said power transistors if they are put into an ON state.
8. The power converter circuit of claim 1 wherein all components except said inductor and said capacitor are integrated on an IC.
9. The power converter circuit of claim 1 wherein one gate controller is provided for each power switch transistor.
10. The power converter circuit of claim 9 wherein said gate controllers are setting the gate voltage of said power switches in a way that said power switches operate in the linear ohmic region if they are put into an ON state.
11. The power converter circuit of claim 10 wherein said gate controllers are setting the gate voltage three times the threshold voltage of said power transistors if they are put into an ON state.
12. The power converter circuit of claim 9 wherein said gate controllers are setting the gate voltage below the threshold voltage of said power switches if they are put into an OFF state.
13. A method to provide over-current protection of a step-down DC-to-DC converter comprising: providing a high-side transistor switch, a low-side transistor switch, an amplifier, a gate controller, a regulator, an inductor, and a capacitor; switch ON high-side switch and switch OFF low-side switch at the same time initiated by said regulator; switch OFF high-side transistor switch and switch ON low-side transistor; switch if current limit is reached, which is sensed by the amplifier; and establish duty cycle by regulator.
14. The method of claim 13 wherein said regulator is controlling the setting the gates of said power switches by pulse-width modulation signals.
15. The method of claim 13 wherein said gate controller is setting the gate voltage below the threshold voltage of said power transistors if they are put into an OFF state.
16. The method of claim 13 wherein said gate controller is setting the gate voltage of said power switches in a way that said power switches operate in the linear ohmic region if they are put into an ON state.
17. The method of claim 16 wherein said gate controller is setting the gate voltage three times the threshold voltage of said power transistors if they are put into an ON state.
18. The method of claim 13 wherein one gate controller for each power transistor switch is controlling the gates of the correspondent transistors.
19. The method of claim 18 wherein said gate controllers are setting the gate voltage below the threshold voltage of said power transistors if they are put into an OFF state.
20. The method of claim 18 wherein said gate controllers are setting the gate voltage of said power switches in a way that said power switches operate in the linear ohmic region if they are put into an ON state.
21. The method of claim 20 wherein said gate controller is setting the gate voltage three times the threshold voltage of said power transistors if they are put into an ON state.
22. A current-limiting boost DC-to-DC power converter, comprising: a power switch connected to on one side to ground and on the other side to an inductor and to a rectifying means; a rectifying means; an amplifying means to amplify the voltage on the on-state source-to-drain resistance of said power switch; a regulator having an input and an output, wherein the input is said amplified voltage and the output are signals to a gate controller to set said power switch ON or OFF depending if said the current through an inductor is exceeding a limit and to achieve a duty cycle keeping the difference between charge/discharge energy to a minimum; a capacitor being connected on one side to ground and on the other side to an output port and to said rectifying means; said inductor being connected on one side to an input voltage source and on the other side to said rectifying means and to said power switch; and said gate controller to control the gate voltage of said power switch having as input signals from said regulator.
23. The power converter circuit of claim 22 wherein said power switch is a NMOS transistor.
24. The power converter circuit of claim 22 wherein said regulator is controlling the setting of said power switch by pulse-width modulation signals.
25. The power converter circuit of claim 22 wherein said gate controller is setting the gate voltage below the threshold voltage of said power switch if it is put into an OFF state.
26. The power converter circuit of claim 22 wherein said gate controller is setting the gate voltage of said power switch in a way that said power switch operates in the linear ohmic region if it is into an ON state.
27. The power converter circuit of claim 22 wherein said gate controller is setting the gate voltage three times the threshold voltage of said power transistor if it is put into an ON state.
28. The power converter circuit of claim 22 wherein all components except said inductor and said capacitor are integrated on an IC.
29. The power converter circuit of claim 22 wherein said rectifying means is a capacitor.
30. A method to provide over-current protection of a boost DC-to-DC converter comprising: providing a power transistor switch, an amplifier, a gate controller, a regulator, an inductor, a rectifying means, and a capacitor; close power transistor switch; sense-voltage on on-state resistance of power transistor switch by an amplifier; open power transistor switch if current limit is reached which is sensed by the amplifier; and establish duty cycle by regulator.
31. The method of claim 30 wherein said regulator is controlling the setting of said power transistor switch by pulse-width modulation signals.
32. The method of claim 30 wherein said gate controller is setting the gate voltage below the threshold voltage of said power transistor switch if tit is put into an OFF state.
33. The method of claim 30 wherein said gate controller sets the gate voltage of said power switch in a way that said power switch operates in the linear ohmic region if it is put into an ON state.
34. The method of claim 30 wherein said gate controller sets the gate voltage three times the threshold voltage of said power transistor if it is put into an ON state.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
June 22, 2004
February 13, 2007
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.