A datum is stored in a memory by placing a memory cell in a first state that is indicative of the datum, and later placing the same or a different cell in a second state that is indicative of the same datum. If a different cell is placed in the second state, both cells are programmed to store the same number of bits, and then preferably the first cell is erased. Preferably, the first cell is placed in the first state by the application thereto of a first train of voltage pulses until the cell's threshold voltage exceeds a first reference voltage, and the first or second cell is placed in the second state by the application thereto of a second train of voltage pulses until the cell's threshold voltage exceeds a second reference voltage.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of storing a datum in a memory, comprising the steps of: (a) placing a cell of the memory in a first state that is indicative of the datum; and (b) placing said cell in a second state that is indicative of the datum, said second state having a longer data retention time than said first state.
2. The method of claim 1 , wherein said cell is placed in said first state by steps including applying at least one first voltage pulse to said cell until a threshold voltage of said cell exceeds a first reference voltage that is indicative of the datum; and wherein said cell is placed in said second state by steps including applying at least one second voltage pulse to said cell until said threshold voltage of said cell exceeds a second reference voltage that is indicative of the datum, said second reference voltage being different from said first reference voltage.
3. The method of claim 2 , wherein said second reference voltage is greater than said first reference voltage.
4. The method of claim 2 , wherein a monotonically increasing plurality of said first voltage pulses are applied to said cell and then a monotonically increasing plurality of said second voltage pulses are applied to said cell.
5. The method of claim 4 , wherein successive said first voltage pulses differ by a common first increment, wherein successive said second voltage pulses differ by a common second increment, and wherein said second increment is less than said first increment.
6. A memory device comprising: (a) at least one cell; and (b) a controller operative: (i) to place one of said at least one cell in a first state that is indicative of a datum, and (ii) to place said one cell in a second state that is indicative of said datum, said second state having a longer data retention time than said first state.
7. A method of storing a datum in a memory that includes a plurality of cells, the method comprising the steps of: (a) placing a first cell of the memory in a first state that is indicative of the datum; and (b) placing a second cell of the memory in a second state that is indicative of the datum, said second state having a longer data retention time than said first state; wherein said first cell and said second cell then store an identical number of bits.
8. The method of claim 7 , further comprising the step of: (c) erasing said first cell.
9. The method of claim 7 , wherein said first cell is placed in said first state by steps including applying at least one first voltage pulse to said first cell until a threshold voltage of said first cell exceeds a first reference voltage that is indicative of the datum; and wherein said second cell is placed in said second state by steps including applying at least one second voltage pulse to said second cell until a threshold voltage of said second cell exceeds a second reference voltage that is indicative of the datum.
10. The method of claim 9 , wherein said second reference voltage is greater than said first reference voltage.
11. The method of claim 9 , wherein a monotonically increasing plurality of said first voltage pulses are applied to said first cell and a monotonically increasing plurality of said second voltage pulses are applied to said second cell.
12. The method of claim 11 , wherein successive said first voltage pulses differ by a common first increment, wherein successive said second voltage pulses differ by a common second increment, and wherein said second increment is less than said first increment.
13. A memory device comprising: (a) an array of cells; and (b) a controller operative: (i) to place a first of said cells in a first state that is indicative of a datum, and (ii) to place a second of said cells in a second state that is indicative of said datum, said second state having a longer data retention time than said first state, wherein said first cell and said second cell then store an identical number of bits.
14. A method of operating a memory that includes a plurality of cells, comprising the steps of: (a) for each of at least one of the cells: (i) comparing a threshold voltage of said each cell to a first reference voltage that is indicative of a certain bit pattern, and (ii) comparing said threshold voltage of said each cell to a second reference voltage that is greater than said first reference voltage and that also is indicative of said bit pattern; and (b) for each said at least one cell, if said comparing shows that said threshold voltage of said each cell is between said first reference voltage and said second reference voltage: applying at least one voltage pulse to said each cell until said threshold voltage of said each cell is greater than said second reference voltage.
15. A memory device comprising: (a) at least one cell; and (b) a controller operative, for each said at least one cell for which a comparison of a threshold voltage of said each cell to a first reference voltage that is indicative of a certain bit pattern and to a second reference voltage that is indicative of said bit pattern shows that said threshold voltage of said each cell is between said first reference voltage and said second reference voltage: to apply at least one voltage pulse to said each cell until said threshold voltage of said each cell is greater than said second reference voltage.
16. A method of operating a memory that includes a plurality of cells, comprising the steps of: (a) for each of at least one of the cells: (i) comparing a threshold voltage of said each cell to a first reference voltage that is indicative of a certain bit pattern, and (ii) comparing said threshold voltage of said each cell to a second reference voltage that is greater than said first reference voltage and that also is indicative of said bit pattern; and (b) for each said at least one cell, if said comparing shows that said threshold voltage of said each cell is between said first reference voltage and said second reference voltage: applying at least one voltage pulse to a corresponding other cell until a threshold voltage of said corresponding other cell is greater than said second reference voltage.
17. The method of claim 16 , further comprising the step of: (c) for each said at least one cell for which said comparing shows that said threshold voltage is greater than said first reference voltage and less than said second reference voltage: subsequent to said applying of said at least one voltage pulse to said corresponding other cell until said threshold voltage of said corresponding other cell is greater than said second reference voltage: erasing said each cell.
18. A memory device comprising: (a) an array of cells; and (b) a controller operative, for each said cell of said array for which a comparison of a threshold voltage of said each cell to a first reference voltage that is indicative of a certain bit pattern and to a second reference voltage that is indicative of said bit pattern shows that said threshold voltage of said each cell is between said first reference voltage and said second reference voltage: to apply at least one voltage pulse to a corresponding other cell of said array until a threshold voltage of said corresponding other cell is greater than said second reference voltage.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 2, 2004
February 13, 2007
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