In a memory system, a memory device that outputs a data strobe signal and memory cell data according to a read command. A memory controller receives the data strobe signal and latches the memory cell data that is output by the memory device, using an interface circuit that realigns the data strobe signal so that an edge of the data strobe signal is substantially centered on the availability of the memory cell data. The interface circuit includes a logic circuit portion that generates a plurality of selection signals in response to the read command and that outputs data strobe sampling signals in response to the selection signals, and further includes a storage portion that captures an edge of the data strobe signal in response to the data strobe sampling signals and that realigns the data strobe signal. Accordingly, the memory controller adaptively latches the data input/output signal by monitoring the data strobe signal provided by the memory device, without including a delay locked loop (DLL) circuit which has a complicated structure and consumes a large amount of power.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory system comprising: a memory device that outputs a data strobe signal and memory cell data according to a read command; and a memory controller that receives the data strobe signal and that latches the memory cell data that is output by the memory device, using an interface circuit that realigns the data strobe signal so that an edge of the data strobe signal is substantially centered on the availability of the memory cell data, wherein the interface circuit comprises: a logic circuit portion that generates a plurality of selection signals in response to the read command and that outputs data strobe sampling signals in response to the selection signals; and a storage portion that captures an edge of the data strobe signal in response to the data strobe sampling signals and that realigns the data strobe signal.
2. The memory system of claim 1 , wherein the logic circuit portion comprises: a plurality of MUXes each selecting one of a previous data strobe sampling signal and the data strobe signal in response to the selection signals and outputting the selected signal; and flip-flops each outputting a current data strobe sampling signal, which is the signal output by each of the MUXes, in response to a clock signal and feeding the current data strobe sampling signal back to a corresponding one of the MUXes so that the current data strobe sampling signal can serve as the previous data strobe sampling signal.
3. The memory system of claim 1 , wherein the storage portion divides a clock signal and a delayed clock signal, which is obtained by delaying the clock signal for a predetermined period of time, into a plurality of regions in each of which states of the clock signal and the delayed clock signal remain constant.
4. The memory system of claim 3 , wherein the storage portion detects in which region of the regions a first rising edge of the data strobe signal occurs.
5. The memory system of claim 1 wherein the storage portion is controlled by a finite state machine (FSM).
6. An interface circuit for receiving a data strobe signal and output data provided by a memory device, the interface circuit comprising: a clock delay portion that receives a clock signal and that produces a delayed clock signal based on the clock signal; a selection signal generating portion that generates first through N-th (where N denotes a natural number) selection signals in response to a read command of the memory device; first through N-th MUXes each selecting one of a previous data strobe sampling signal and the data strobe signal in response to each of the first through N-th selection signals and outputting the selected signal; a first group of flip-flops each outputting a current data strobe sampling signal, which is the signal output by each of the first through N/2-th MUXes, in response to the clock signal and feeding the current data strobe sampling signal back to each of the first through N/2-th MUXes so that the current data strobe sampling signal can serve as the previous data strobe sampling signal of each of the first through N/2-th MUXes; and a second group of flip-flops each outputting a current data strobe sampling signal, which is the signal output by each of the (N/2+1)th through N-th MUXes, in response to the delayed clock signal and feeding the current data strobe sampling signal back to each of the (N/2+1)th through N-th MUXes so that the current data strobe sampling signal can serve as the previous data strobe sampling signal of each of the (N/2+1)th through N-th MUXes.
7. The interface circuit of claim 6 , wherein the interface circuit is provided in a memory controller connected with the memory device.
8. The interface circuit of claim 6 , wherein different edges of the data strobe signal are captured depending on the data strobe sampling signals, and wherein the data strobe signal is recognized so that the edges of the data strobe signal are centered on the output data of the memory device.
9. The interface circuit of claim 6 , further comprising a storage portion that divides the clock signal and the delayed clock signal into a plurality of regions in each of which states of the clock signal and the delayed clock signal remain constant.
10. The interface circuit of claim 9 , wherein the region of the region in which a first rising edge of the data strobe signal of the memory device occurs is detected.
11. The interface circuit of claim 10 , wherein the data strobe signal is realigned so that edges of the recognized data strobe signal are substantially centered on the availability output data of the memory device.
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September 16, 2005
February 20, 2007
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