Nano-machining for circuit edits through the front side or backside of an integrated circuit may be performed using a scanning probe system. The system may create access holes with smaller dimensions and facilitate nano-machining endpoint detection in some embodiments.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method comprising: machining a hole on an integrated circuit with a scanning probe system; and performing a circuit edit through the hole formed by said system.
2. The method of claim 1 including machining said hole on the backside of the integrated circuit.
3. The method of claim 2 including machining a hole as a series of progressively smaller trenches through the backside of a silicon wafer.
4. The method of claim 3 including detecting an open circuit when the tool reaches an isolation region.
5. The method of claim 3 including detecting a short circuit when the tool reaches a metallization.
6. The method of claim 1 including providing an electrical connection between said integrated circuit and said tool.
7. The method of claim 1 including covering a portion of said hole with an insulating layer.
8. The method of claim 7 including covering said hole with an insulating layer before exposing a metallization.
9. The method of claim 1 including spring biasing a cantilever of an atomic force microscopy tool against an integrated circuit.
10. A method comprising: forming a first trench having sidewalls and a bottom in a semiconductor structure using a scanning probe system; forming a second trench through said bottom, said second trench having sidewalls that are spaced more closely than the sidewalls of said first trench; and using said trench to perform a circuit edit.
11. The method of claim 10 including biasing an atomic force microscopy tip against the semiconductor surface to move atomic layers to form said trenches.
12. The method of claim 11 providing an electrical connection between said semiconductor structure and said tip.
13. The method of claim 12 including detecting an open circuit when said tip reaches an isolation region in said semiconductor structure.
14. The method of claim 12 including detecting a short circuit once the tip reaches a metallization in said semiconductor structure.
15. The method of claim 11 including spring biasing said tip against said structure using a cantilever.
16. The method of claim 15 including determining the position of said tip by reflecting a laser beam from said cantilever.
17. The method of claim 10 including covering said first and second trenches with an insulating layer.
18. The method of claim 17 including covering said trenches with an insulating layer before exposing a metallization.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 19, 2004
February 27, 2007
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