Patentable/Patents/US-7185040
US-7185040

Apparatus and method for calculation of divisions and square roots

PublishedFebruary 27, 2007
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

Non-restoring radix-2 division and square rooting procedures are provided. The proposed procedures utilize a quotient/root digit set {−1, 0, +1} and a quotient/root prediction table (QRT/RPT). The i'th quotient/root digit is determined with reference to a partial remainder from (i−2)'th iterative operation and by the quotient/root prediction table. The present procedures generate the (i−1)'th correction term, which is to be applied in calculating the i'th partial remainder, simultaneously with the (i−2)'th correction term, and need not to perform an iterative operation to obtain the i'th partial remainder.

Patent Claims
11 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. An apparatus providing a square root of a radicand by a iterative operation the apparatus comprising: a root digit selector for selecting an (i−1)'th root digit from an (i−2)'th partial remainder; a first correction term generator for creating a first correction term by means of an (i−2)'th partial square root and the (i−1)'th root digit; a second correction term generator for creating a second correction term by means of an (i−1)'th partial square root; a third correction term generator for creating a third correction term by means of the (i−1)'th partial square root; a first subtractor for deducting the first and second correction terms from a left-shifted value of an (i−2)'th partial remainder; a second subtractor for deducting the first and second correction terms from the left-shifted value of the (i−2)'th partial remainder; a carry propagation detector for determining whether there is a borrow or a carry-in while calculating an (i−i )'th partial remainder; root digit prediction means for predicting an i'th root digit in response to an (i−1)'th root digit, the (i−2)'th partial remainder, and an output of the carry propagation detector; and selection means for selecting an alternative one of outputs of the first and second subtractors as an i'th partial remainder in response to the i'th root digit.

2

2. The apparatus according to claim 1 , wherein the second correction term is a conditional correction term when the i'th root digit is +1, and the third correction term is a conditional correction term when the i'th root digit is −1.

3

3. The apparatus according to claim 1 , wherein the root digit prediction means comprises: a first root prediction block for predicting a first root digit in response to the (i−1)'th root digit and the (i−2)'th partial remainder; a second root prediction block for predicting a second root digit in response to the (i−1)'th root digit and the (i−2)'th partial remainder; and a multiplexer for selecting an alternative one of the first and second root digits as the i'th root digit in response to the output of the carry propagation detector.

4

4. The apparatus according to claim 1 , further comprising a storage circuit for storing the (i−1)'th root digit, the (i−2)'th partial remainder, the i'th root digit, and the i'th partial remainder.

5

5. The apparatus according to claim 1 , further comprising a storage circuit for storing the (i−2)'th partial remainder, the (i−2)'th partial square root, the (i−1)'th partial square root, and the i'th partial square root.

6

6. An apparatus operating a square root, the apparatus comprising: an iterative square-rooting circuit for operating a partial remainder involved in x (i) =4x (i−2) −(2q (i−2) +q −(i−1) 2 −i+1 )q −(i−1) −2(2q (i−1) +q −i 2 −i )q −i , where x (i) is an i'th partial remainder, x (i−1) is an (i1)'th partial remainder, x (i−2) is an (i−2)'th partial remainder, q −i is an i'th root digit, q −(i−1) is an (i−1)'th root digit, q (i−1) is an (i−1)'th partial square root q (i−2) is an (i−2)'th partial square root, x (0) =z−1 , and q −i ∈{−1, 0, +1}; a root digit selector for selecting the (i−1)'th root digit from the (i−2)'th partial remainder; a carry propagation detector for checking a presence of a borrow or a carry-in while calculating an (i−1)'th partial remainder; and a root digit prediction block for predicting an i'th root digit in response to the (i−1)'th root digit, the (i−2)'th partial remainder, and an output of the carry propagation detector.

7

7. The apparatus according to claim 6 , further comprising a storage circuit for storing the (i−2)'th partial remainder, the i'th partial remainder, the (i−2)'th partial square root, and an i'th partial square root.

8

8. The apparatus according to claim 6 , wherein the apparatus is associated with a floating point.

9

9. The apparatus according to claim 6 , wherein the iterative square-rooting circuit comprises: a first correction term generator for creating a first correction term by means of an (i−2)'th partial square root and the (i−1)'th root digit; a second correction term generator for creating a second correction term by means of an (i−1)'th partial square root; a third correction term generator for creating a third correction term by means of the (i−1)'th partial square root; a first subtractor for deducting the first and second correction terms from a left-shifted value of an (i−2)'th partial remainder; a second subtractor for deducting the first and second correction terms from the left-shifted value of the (i−2)'th partial remainder; a carry propagation detector for checking there is a borrow or a carry-in while calculating an (i−1)'th partial remainder; root digit prediction means for predicting the i'th root digit in response to an (i−1)'th root digit, the (i−2)'th partial remainder, and an output of the carry propagation detector; and selection means for selecting an alternative one of outputs of the first and second subtractors as the i'th partial remainder in response to the i'th root digit.

10

10. The apparatus according to claim 9 , wherein the second correction term is a conditional correction term when the i'th root digit is +1, and the third correction term is a conditional correction term when the i'th root digit is −1.

11

11. The apparatus according to claim 9 , wherein the root digit prediction means comprises: a first root prediction block for predicting a first root digit in response to the (i−1)'th root digit and the (i−2)'th partial remainder; a second root prediction block for predicting a second root digit in response to the (i−1)'th root digit and the (i−2)'th partial remainder; and a multiplexer for selecting an alternative one of the first and second root digits as the i'th root digit in response to the output of the carry propagation detector.

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Patent Metadata

Filing Date

October 1, 2002

Publication Date

February 27, 2007

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