Failsafe control circuit for electrical appliances whereby at least one electrical load (10) is activated, the control circuit comprising logic control means (1), operation switching means (8) between said electrical load (10) and a supply voltage (V), and a first drive circuit (6) which receives a first command signal (4) from the logic control means (1), said first drive circuit (6) acting on said operation switching means (8). It also comprises security switching means (9) between the electrical load (10) and the supply voltage (V), and a second drive circuit (7) which receives a second command signal (5) from the logic control means (1), said second drive circuit (7) acting on the security switching means (9) so that it closes said security switching means (9) only if said second command signal (5) is a pulse signal.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A failsafe control circuit for electrical appliances whereby at least one electrical load ( 10 ) is activated, the control circuit comprising logic control means ( 1 ), operation switching means ( 8 ) between said electrical load ( 10 ) and a supply voltage (V), and a first drive circuit ( 6 ) which receives a first command signal ( 4 ) from the logic control means ( 1 ), said first drive circuit ( 6 ) acting on said operation switching means ( 8 ), security switching means ( 9 ) between the electrical load ( 10 ) and the supply voltage (V), and a second drive circuit ( 7 ) which receives a second command signal ( 5 ) from the logic control means ( 1 ), said second drive circuit ( 7 ) acting on the security switching means ( 9 ) so that it closes said security switching means ( 9 ) only if said second command signal ( 5 ) is a pulse signal.
2. The failsafe control circuit according to claim 1 , wherein the security switching means ( 9 ) comprise a power relay with a coil (K 2 ), and the drive circuit ( 7 ) comprises a monostable circuit which acts on said coil (K 2 ), so that it only permits a current to flow through the coil (K 2 ) of the security switching means ( 9 ) if the second command signal ( 5 ) is a pulse signal at a frequency higher than a pre-established minimum frequency.
3. The failsafe control circuit according to claim 1 , wherein at least one of the switching means ( 8 , 9 ) comprises a triac.
4. The failsafe control circuit according to claim 1 , wherein it also comprises security switching means ( 13 ) between the first and second drive circuits ( 6 , 7 ) and its supply voltage (V 2 ), and comprises a third drive circuit ( 12 ) which receives a third command signal ( 11 ), so that said drive circuit ( 12 ) closes said security switching means ( 13 ) only if the third command signal ( 11 ) is a pulse signal.
5. The failsafe control circuit according to claim 1 , wherein a maximum operating time is set, after which the electrical load ( 10 ) is no longer energized.
6. The failsafe control circuit according to claim 2 , wherein the monostable circuit comprises a transistor connected in series with the coil (K 2 ) and a capacitor (C 1 ) which filters the second command signal ( 5 ) before it reaches said transistor.
7. The failsafe control circuit according to claim 2 , wherein the operation switching means ( 8 ) comprise a power relay with a coil (K 1 ), and the drive circuit ( 6 ) comprises a transistor (T 1 ) connected in series with said coil (K 1 ).
8. The failsafe control circuit according to claim 5 , wherein the maximum operating time is determined in accordance with the power that is being supplied to the electrical load ( 10 ).
9. The failsafe control circuit according to claim 7 , wherein the first command signal ( 4 ) is also a pulse signal.
10. The failsafe control circuit according to any of claims 1 , 2 or 6 , wherein the operation switching means ( 8 ) comprise a triac.
11. The failsafe control circuit according to claim 6 , wherein the operation switching means ( 8 ) comprise a power relay with a coil (K 1 ), and the drive circuit ( 6 ) comprises a transistor (T 1 ) connected in series with said coil (K 1 ).
12. The failsafe control circuit according to claim 9 , wherein there is a phase difference between the first command signal ( 4 ) and the second command signal ( 5 ), so that the overlap of energy which has to be supplied to coil (K 1 ) and coil (K 2 ) is reduced.
13. The failsafe control circuit according to claim 11 , wherein the first command signal ( 4 ) is also a pulse signal.
14. The failsafe control circuit according to claim 13 , wherein there is a phase difference between the first command signal ( 4 ) and the second command signal ( 5 ), so that the overlap of energy which has to be supplied to coil (K 1 ) and coil (K 2 ) is reduced.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 27, 2004
March 6, 2007
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