A circuit configuration for testing a circuit using a test device for providing a test mode, where test procedures are performed sequentially. The test procedures involve comparing actual data that are output by the circuit under test with prescribed nominal data in the test device. A combinational logic device for logically combining the sequentially output test results is provided such that result data indicate fault free operation of the circuit under test only if the actual data which are output match the prescribed nominal data in all of the sequentially performed test procedures. The result data is output via an addressing and control unit in the circuit under test.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A circuit configuration for testing a circuit, the circuit having at least one memory cell array and at least one addressing and control unit, the circuit configuration comprising: a test data line connected to the circuit under test; a test device for providing a test mode and connected to said test data line, said test device having a test mode unit for producing test data supplied to the circuit under test through said test data line, said test device performing test procedures sequentially, the test procedures involving actual data output by the circuit under test on a basis of the test data and the actual data being compared with prescribed nominal data in said test mode unit; a result data line for sequentially outputting test results obtained using the test procedures on a basis of the comparison; and a combinational logic device for logically combining the test results output sequentially to produce an overall result data such that the overall result data indicates fault free operation of the circuit under test only if the actual data being output match the prescribed nominal data in all of the sequentially performed test procedures, the overall result data being output through an addressing and control line by the addressing and control unit of the circuit under test.
2. The circuit configuration according to claim 1 , wherein said combinational logic device has a result memory unit connected to said result data line and stores the overall result data and logically combines current test results obtained sequentially with the overall result data.
3. The circuit configuration according to claim 2 , wherein said combinational logic device has a control logic unit for updating said result memory unit and is connected to said result memory unit.
4. The circuit configuration according to claim 2 , wherein said result memory unit is a single-bit memory.
5. The circuit configuration according to claim 1 , wherein said combinational logic device has an output data line connected to and outputting the overall result data to the addressing and control unit.
6. The circuit configuration according to claim 3 , wherein said combinational logic device has a read signal line connected to and supplying a read signal to said control logic unit.
7. The circuit configuration according to claim 1 , wherein said test data line contains 4, 8 or 16 individual lines.
8. The circuit configuration according to claim 1 , further comprising a single chip and the circuit under test, said test device and said combinational logic device are disposed on said single chip.
9. The circuit configuration according to claim 1 , wherein said result data line for sequentially outputting the test results obtained using the test procedures contains a single individual line.
10. A method for testing a circuit having at least one memory cell array and at least one addressing and control unit, which comprises the steps of: initiating a test mode using a test device; producing test data in a test mode unit in the test device; supplying the test data from the test device to the circuit under test through a test data line; performing test procedures sequentially, the test procedures involving actual data being output by the circuit under test on a basis of the test data and the actual data being compared with prescribed nominal data in the test mode unit; obtaining test results using the test procedures on a basis of the comparison; outputting sequentially the test results through a result data line; logically combining the test results resulting in an overall result data using a combinational logic device such that the overall result data indicates fault free operation of the circuit under test only if the actual data output match the prescribed nominal data in all of the sequentially performed test procedures; and outputting the overall result data through the addressing and control line of the addressing and control unit of the circuit under test.
11. The method according to claim 10 , which further comprises: continuously logically combining current test results with the overall result data for updating the overall result data; and storing the overall result data in the result memory unit.
12. The method according to claim 11 , which further comprises updating the result memory unit using a control logic unit in the combinational logic device.
13. The method according to claim 11 , which further comprises storing the overall result data sequentially obtained in the result memory unit in the combinational logic device as a single-bit information item.
14. The method according to claim 10 , which further comprises outputting the overall result data to the addressing and control unit through an output data line connected to the combinational logic device.
15. The method according to claim 12 , which further comprises supplying the control logic unit in the combinational logic device with a read signal through a read signal line connected to the combinational logic device.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 12, 2004
March 6, 2007
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