A ferroelectric memory device capable of structurally reducing data deterioration. In this ferroelectric memory device, bitlines are hierarchized, and sub-bitlines subordinate to the bitlines through sub-bitline select switches are provided in each of a plurality of block regions. The block regions are sequentially selected along an increment direction, and wordlines in each block are sequentially selected along the increment direction from the lowest wordline to the highest wordline. The number “n” of wordlines arranged in each block region is set equal to or less than a predetermined limit number about relaxation.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A ferroelectric memory device comprising: a memory cell array region divided into a plurality of block regions; a plurality of wordlines arranged in parallel along a first direction within the memory cell array region; a plurality of bitlines arranged in parallel along a second direction intersecting the first direction, within the memory cell array region; a plurality of sub-bitlines provided for each of the bitlines in each of the block regions; a sub-bitline select switch provided between each of the sub-bitlines and corresponding one of the bitlines; a plurality of ferroelectric memory cells respectively disposed at intersections between the sub-bitlines and the wordlines; a first driver section which drives the wordlines and the sub-bitline select switches; and a second driver section which drives the bitlines, wherein the first driver section selects one of the wordlines sequentially in the second direction, and turns on the sub-bitline select switches connected to the sub-bitlines intersecting the selected one of the wordlines; and wherein the number of the wordlines in each of the block regions is set equal to or less than a predetermined limit number of times for preventing excessive relaxation of the ferroelectric memory cells.
2. The ferroelectric memory device as defined in claim 1 , wherein the predetermined limit number is a maximum number of times an unselected voltage is allowed to be applied when logic of data deteriorated by the repeated application of the unselected voltage with the same polarity to the ferroelectric memory cells, is determined to be the same as the logic of the original data before deterioration by a sense amplifier connected to the bitlines when reading the data.
3. A display driver IC comprising: the ferroelectric memory device as defined in claim 1 ; and a driver section which is driven based on data read from the ferroelectric memory device.
4. A ferroelectric memory device comprising: a plurality of memory cell array regions; a plurality of wordlines arranged in parallel along a first direction within each of the memory cell array regions; a plurality of bitlines arranged in parallel along a second direction intersecting the first direction, within each of the memory cell array regions; a plurality of ferroelectric memory cells respectively disposed at intersections between the wordlines and the bitlines within each of the memory cell array regions; a first driver section which drives the wordlines within each of the memory cell array regions; and a second driver section which drives the bitlines within each of the memory cell array regions, wherein the memory cell array regions are arranged along the second direction, and the first driver section selects one of the wordlines sequentially in the second direction within each of the memory cell array regions; and wherein the number of the wordlines within each of the memory cell array regions is set equal to or less than a predetermined limit number of times for preventing excessive relaxation of the ferroelectric memory cells.
5. The ferroelectric memory device as defined in claim 4 , wherein the predetermined limit number is a maximum number of times an unselected voltage is allowed to be applied when logic of data deteriorated by the repeated application of the unselected voltage with the same polarity to the ferroelectric memory cells, is determined to be the same as the logic of the original data before deterioration by a sense amplifier connected to the bitlines when reading the data.
6. A display driver IC comprising: the ferroelectric memory device as defined in claim 4 ; and a driver section which is driven based on data read from the ferroelectric memory device.
7. A ferroelectric memory device comprising: a first memory cell array; a second memory cell array; and a data buffer which writes data read from the first memory cell array into the second memory cell array; wherein each of the first and second memory cell arrays includes: a plurality of wordlines arranged in parallel along a first direction and sequentially selected in a second direction which intersects the first direction; a plurality of wordlines arranged in parallel along a first direction and sequentially selected in a second direction which intersects the first direction; a plurality of bitlines arranged in parallel along the second direction and connected to the data buffer; and a plurality of ferroelectric memory cells respectively disposed at intersections between the wordlines and the bitlines; wherein at least one of the ferroelectric memory cells connected to one of the wordlines within the first memory cell array is set into a state in which a first logical value is written by reading one of the first logical value and a second logical value stored in the at least one of the ferroelectric memory cells; and wherein the second logical value read from the first memory cell array is written into at least one of the ferroelectric memory cells connected to one of the wordlines within the second memory cell array, the first logical value being previously stored in the at least one of the ferroelectric memory cells.
8. The ferroelectric memory device as defined in claim 7 , wherein the data buffer writes data read from the second memory cell array into the first memory cell array.
9. The ferroelectric memory device as defined in claim 7 , wherein at least one of the ferroelectric memory cells connected to one of the wordlines within one of the first and second memory cell arrays is set into a state in which a first logical value is written by reading one of the first logical value and a second logical value stored in the at least one of the ferroelectric memory cells; and wherein the second logical value read from one of the first and second memory cell arrays is written into at least one of the ferroelectric memory cells connected to one of the wordlines within the other of the first and second memory cell arrays, the first logical value being previously stored in the at least one of the ferroelectric memory cells.
10. The ferroelectric memory device as defined in claim 7 , wherein each of the first and second memory cell arrays is divided into a plurality of block regions; wherein each of the first and second memory cell arrays further includes: a plurality of sub-bitlines provided for each of the bitlines in each of the block regions; and a sub-bitline select switch provided between each of the sub-bitlines and corresponding one of the bitlines; wherein the ferroelectric memory cells are respectively disposed also at intersections between the sub-bitlines and the wordlines; and wherein the number of the wordlines in each of the block regions is set equal to or less than a predetermined limit number of times for preventing excessive relaxation of the ferroelectric memory cells.
11. The ferroelectric memory device as defined in claim 7 , further comprising: a third memory cell array which includes a plurality of wordlines, a plurality of bitlines, and a plurality of ferroelectric memory cells, wherein the data buffer writes data read from the second memory cell array into the third memory cell array, and writes data read from the third memory cell array into the first memory cell array.
12. The ferroelectric memory device as defined in claim 11 , wherein at least one of the ferroelectric memory cells connected to one of the wordlines within one of the first to third memory cell arrays is set into a state in which a first logical value is written by reading one of the first logical value and a second logical value stored in the at least one of the ferroelectric memory cells; and wherein the second logical value read from one of the first to third memory cell arrays is written into at least one of the ferroelectric memory cells connected to one of the wordlines within another one of the first to third memory cell arrays, the first logical value is previously stored in the at least one of the ferroelectric memory cells.
13. The ferroelectric memory device as defined in claim 11 , wherein each of the first to third memory cell arrays is divided into a plurality of block regions; wherein each of the first to third memory cell arrays further includes: a plurality of sub-bitlines provided for each of the bitlines in each of the block regions; and a sub-bitline select switch provided between each of the sub-bitlines and corresponding one of the bitlines; wherein the ferroelectric memory cells are respectively disposed also at intersections between the sub-bitlines and the wordlines; and wherein the number of the wordlines in each of the block regions is set equal to or less than a predetermined limit number of times for preventing excessive relaxation of the ferroelectric memory cells.
14. A display driver IC comprising: the ferroelectric memory device as defined in claim 7 ; and a driver section which is driven based on data read from the ferroelectric memory device.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 7, 2004
March 13, 2007
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